Hello all, I am planning to work on Fidus side winger 100 (https://www.xilinx.com/products/boards-and-kits/1-o1x8yv.html) ZYNQ Ultraplus board for PCI gen 4 RTL testing. I will be using my PCI controller + ZYNQ serdes.
I am unable to find serdas IP in VIVAO. There is intergrated block of (PCI GEN3 + serdes) but not seperate serdes. How can I add serdes to my VIVADO project.
Try using Xilinx GT wizard for PCIe protocol.