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ZYNQ eMMC SDIO errors: Timing or Signal Integrity issue?

I am using Xillix's ZYNQ p/n XC7Z030-2SBG485I along with Micron's eMMC p/n MTFC16GJDDQ-4M IT.
Mediating between them is the same level shifter as in Xillinx's eval-board, TI's p/n TXS02612RTWR.
The level shifter shifts between 3.3V (eMMC) to 2.5V (ZYNQ-MIO).
Due to mechanical limitations, the eMMC is placed aproximatly 10" (inch) from the ZYNQ.
The level shifter is place less than an inch from the eMMC.
The SDIO bus passes through a flex-rigid PCB along with impedance matching ground.

During 50 MHz SDIO clk operation, the SDIO bus encounters many errors preventing the board from booting its BSP/OSN properly.
When decreasing the SDIO clk frequency to 8 MHz, the BSP/OS loads properly.
Temperature effect: at temperature lower than 5 deg. cel. SDIO errors return.

According to your experience:
1. Are the SDIO errors likely to be caused by a timing problem (a very short hold time) or by a Signal Integrity problem?
   FYI, the SDIO_CLK rise time is ~ 2-3nsec, hold time is ~3nsec measured at the load (eMMC).
2. Other level shifters (such as TI's p/n TXS0206) have a Clock Feedback pin to host for resynchronizing data to the processor. Does Xillinx/ZYNQ support such functionality?

Could you guide me to a solution?

Best Regards,


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1 Reply
Community Manager
Community Manager
Registered: ‎07-23-2012

#1 Yes, it looks like you are hitting timing issues as the hardware was working at different temperature.
#2 As far as I know SDIO controller doesn't have feedback clock.

Can you please perform IBIS simulations to understand the issue better?
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

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