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j1398830
Newbie
Newbie
1,025 Views
Registered: ‎05-18-2018

ZYNQ7 AXI clocks must be equal?

Hi, I'm trying to connect a ZYNQ7 processing system block in the IP integrator in Vivado 2018.2 to a simple RTL design with AXI ports. The RTL runs in 40 MHz, and I've have configured the FCLK_CLK0 output to generate a 40 MHz clock. But when I connect that clock to the AXI clock inputs for the processing system I get the following cryptic warnings:

WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter PCW_M_AXI_GP0_FREQMHZ(10) on '/processing_system7_0' with propagated value(40). Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter PCW_S_AXI_HP0_FREQMHZ(10) on '/processing_system7_0' with propagated value(40). Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter PCW_S_AXI_HP2_FREQMHZ(10) on '/processing_system7_0' with propagated value(40). Command ignored

I also get warnings like:

WARNING: [BD 41-927] Following properties on pin /cache_wrapper_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=computer_processing_system7_0_1_FCLK_CLK0

What does this mean? That the input for the AXI ports on the processing system must be 100 MHz (or 10 MHz?)? Must I use an external AXI clock converter to connect my RTL to the processing system?

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pvenugo
Moderator
Moderator
997 Views
Registered: ‎07-31-2012

Hi @j1398830,

 

You may want to check https://www.xilinx.com/support/answers/70040.html for solution.

 

Regards

Praveen


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j1398830
Newbie
Newbie
976 Views
Registered: ‎05-18-2018

Thanks, I did not however upgrade from Vivado 2017.3 so I don't think it's the same bug. I have, however, tried to replace the PS block, but the warning remain. I also get the warnings when placing a PS block in a new and empty project, which seems strange...

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