05-12-2014 12:07 AM
I wonder if it's possible to read the DDR3 memory with a custom ip core axi4-lite master interface connected to an interconnect then connected to the HP zynq port ? (as shown in the picture)
Because I'm trying since 3 or 4 weeks to do that and that's give me wrong things.
(I use an ILA to see what's happen on the master/slave communication.)
I write DDR3 in SDK via ps : Xil_Out32(DDR_BASE_ADDRESS, 0x00000001); so @ 0x10000000 write 0x00000001.
Then I want to read this data via my PL custom ip(this ip is just a redirection): Xil_Out32(MY_IP_BASE_ADDRESS, DDR_BASE_ADDRESS); so I send to my ip the address to read.
And then I read my ip register which normally store the data : data = Xil_In32(MY_IP_BASE_ADDRESS + REGISTER_1); so read address 0x43C00004 and the data is not 0x00000001 but 0x9FA90DDC;
Someone can help me to understand ?
I use Vivado 2013.4 on windows 7 machine.
Thanks for your help,