cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
3,253 Views
Registered: ‎02-18-2014

Zedboard DDR3 memory

Jump to solution

Hi everyone,

 

I wonder if it's possible to read the DDR3 memory with a custom ip core axi4-lite master interface connected to an interconnect then connected to the HP zynq port ? (as shown in the picture)

 

Because I'm trying since 3 or 4 weeks to do that and that's give me wrong things.

 

block_design.jpg

(I use an ILA to see what's happen on the master/slave communication.)

 

I write DDR3 in SDK via ps : Xil_Out32(DDR_BASE_ADDRESS, 0x00000001); so @ 0x10000000 write 0x00000001.

 

Then I want to read this data via my PL custom ip(this ip is just a redirection): Xil_Out32(MY_IP_BASE_ADDRESS, DDR_BASE_ADDRESS); so I send to my ip the address to read.

 

 And then I read my ip register which normally store the data : data = Xil_In32(MY_IP_BASE_ADDRESS + REGISTER_1); so read address 0x43C00004 and the data is not 0x00000001 but 0x9FA90DDC;

 

 

Someone can help me to understand ?

 

I use Vivado 2013.4 on windows 7 machine.

 

Thanks for your help,

 

Best regards.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Contributor
Contributor
4,109 Views
Registered: ‎02-18-2014

Re: Zedboard DDR3 memory

Jump to solution
0 Kudos
2 Replies
Highlighted
Contributor
Contributor
4,110 Views
Registered: ‎02-18-2014

Re: Zedboard DDR3 memory

Jump to solution
0 Kudos
Highlighted
Newbie
Newbie
2,236 Views
Registered: ‎05-19-2010

Re: Zedboard DDR3 memory

Jump to solution

Hi , 

how did you do that?

 

Thanks 

0 Kudos