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Visitor
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Registered: ‎05-17-2019

Zedboard clock configuration - range(MHZ) form -2 to -1 in Vivado 2018.3

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Frequency range {-2, -1} when using zedboard preset only in vivado 2018.3

Hello, 

I have a strange problem. I am creating a new project for Zedboard, adding the Zynq7 processing system IP and trying to configure it (Current preset: Zedboard, tab Clock Configuration).

In vivado 2018.1 i have normal ranges like:

DDR - 200.000000 : 534:000000

FCLK_CLK0 - 0.100000 : 250.000000

 

While in the Vivado 2018.3 the above ranges are from -2: -1. 

Because of that, I cannot set the FCLK_CLK0 frequency for example to 75 MHZ because Vivado shows the Validation error param PCW_FPGA0_PERIPHERAL_FREQMHZ 75.000000 is out of the range {-2, -1}

 

Should I do something more? Did something change in Vivado 2018.3?

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Moderator
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Registered: ‎10-30-2017

Re: Zedboard clock configuration - range(MHZ) form -2 to -1 in Vivado 2018.3

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Hi @jan_ch ,

 

Please check my below screen shot. I took Zed board as template but I could not see what you are talking about. Please send me the test case for it. I will check and update again.

freq_check.PNG

 

Best Regards,
Srikanth
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Registered: ‎10-30-2017

Re: Zedboard clock configuration - range(MHZ) form -2 to -1 in Vivado 2018.3

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Hi @jan_ch ,

I do not see this behaviour at my end. The FCLK_CLK0 range is still 0.1000000 to 250.000 only. I aslo took the Zedboard template and verified this. I think there is something is missing at your end. Please cross verify it once. I am able to set the 75MHz clock for FCLK_CLK0 and validation is successful without any issue. In case if you are upgrading your design from 2018.1 to 2018.3 then I think there is some thing is missed while upgrading the design. in this case please remove the Zynq and add it again and configure it.


Best Regards,
Srikanth
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Visitor
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Registered: ‎05-17-2019

Re: Zedboard clock configuration - range(MHZ) form -2 to -1 in Vivado 2018.3

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Hello, I am not upgrading. I am creating design from scratch. The design is for zedboard, then in block desing I am adding Zynq PS IP core, and trying to configure it. I have checked it on my home workstation with webpack as well as in the university with the full license. Every time in 2018.3 i have almost all the ranges from -2 to -1 while in 2018.1 there are normal ranges. 

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Registered: ‎10-30-2017

Re: Zedboard clock configuration - range(MHZ) form -2 to -1 in Vivado 2018.3

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Hi @jan_ch ,

 

Please check my below screen shot. I took Zed board as template but I could not see what you are talking about. Please send me the test case for it. I will check and update again.

freq_check.PNG

 

Best Regards,
Srikanth
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.

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Visitor
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Registered: ‎05-17-2019

Re: Zedboard clock configuration - range(MHZ) form -2 to -1 in Vivado 2018.3

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Hi, I've recreated the design in order to prepare bd.tcl for you, but now everything works.. I have no idea what i did wrong later. Thanks for Your help, and I will accept your last post as a solution.

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Participant
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Registered: ‎11-10-2016

Re: Zedboard clock configuration - range(MHZ) form -2 to -1 in Vivado 2018.3

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I currently have the same problem in both Vivado 2018.3 and 2019.1.

Steps to reproduce on my machine: Ubuntu 18.04, Vivado 2018.3 or 2019.1

  1. "File -> Project -> New..."
  2. Select part "xc7z010clg400-1"
  3. "Create Block Design"
  4. "Add IP...", "ZYNQ7 Processing System"
  5. "Customize Block..."

All sorts of ranges (including for FCLK_CLK0) are now from -2 to -1.

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Participant
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Registered: ‎11-10-2016

Re: Zedboard clock configuration - range(MHZ) form -2 to -1 in Vivado 2018.3

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You're viewing the "Advanced Clocking" tab there, not the "Basic Clocking" tab. The ranges are wrong in the latter (on my machine).
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Visitor
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Registered: ‎12-29-2019

Re: Zedboard clock configuration - range(MHZ) form -2 to -1 in Vivado 2018.3

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I can confirm the same behaviour on my machine (debian). Same steps, same same result (Vivado 2019.2). In fact I can not set any frequency, even the input frequency tab can not be changed because its input frequency range too is -2 : -1

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Visitor
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Registered: ‎12-29-2019

Re: Zedboard clock configuration - range(MHZ) form -2 to -1 in Vivado 2018.3

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Just on the "I have no Idea what I'm doing" side. opening the 

ip/system_processing_system7_0_2/system_processing_system7_0_0.xml file yields those faulty 

spirit:minimum="-2" spirit:maximum="-1" 

entryies all over the file (84 of them).

changing the 

<spirit:name>PCW_UIPARAM_ACT_DDR_FREQ_MHZ</spirit:name>
<spirit:displayName>PCW UIPARAM ACT DDR FREQ MHZ</spirit:displayName>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_ACT_DDR_FREQ_MHZ" spirit:order="26500" spirit:minimum="-2" spirit:maximum="-1">533.333374</spirit:value>

entry to spirit:minimum="-2" -> spirit:minimum="100"

and  spirit:maximum="-1" -> spirit:maximum="533"

seems to have solved this problem. in the block design, vivado sees that the ip has changed in some way. Regenerating the IP seems to overwrite those wacky changes in the the xml file whilest also getting rid of most of the other, seemingly invalid, min max entries. 

only 2 remain now:

<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN0_PERIPHERAL_FREQMHZ" spirit:order="24700" spirit:minimum="-2" spirit:maximum="-1">-1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_CAN0_PERIPHERAL_FREQMHZ">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PCW_CAN1_PERIPHERAL_FREQMHZ</spirit:name>
<spirit:displayName>PCW CAN1 PERIPHERAL FREQMHZ</spirit:displayName>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN1_PERIPHERAL_FREQMHZ" spirit:order="24800" spirit:minimum="-2" spirit:maximum="-1">-1</spirit:value>

I'll try to reproduce the faulty project file again to upload the faulty ip file. 

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Visitor
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Registered: ‎12-29-2019

Re: Zedboard clock configuration - range(MHZ) form -2 to -1 in Vivado 2018.3

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Interestingly I was not able to reproduce the faulty behaviour. However, when it will show up again, I'll upload the faulty File. 

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