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fpga_newbee99
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Visitor
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Registered: ‎01-25-2021

ZynQ Verification and Debug for Peaked IP

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Hi everyone,

I am currently working on a project on ZedBoard with ZynQ 7000 series. I try to simulate the PS (along with C code)  and PL on Vivado 2018.1 to verify and debug my packed IP. And I found some related questions about my prolem:

Along to this article https://forums.xilinx.com/t5/Simulation-and-Verification/ZYNQ-PS-and-PL-simulation/td-p/487540, the only way to simulate both PS and PL is to use the Verification IP (VIP) of Xilinx. But by that way, I can not associate .ELF file to check whether my C code are working properly or not! So I have some following questions:

1. Will the VIP be called automatically when simulation if my block design used ZynQ?

2. Is there another way that can simulate my PS(code C) + PL on Vivado without using the board? (Like Microblaze did)

Note: I also found that Hardware In The Loop (HIL) Simulation for the Zynq-7000 can help me but still need to implement the PL on the Board before simulation on ISIM. This is 

Hope to see any ideas about my problem or some relevant docs.

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abouassi
Moderator
Moderator
314 Views
Registered: ‎03-25-2019

Hi @fpga_newbee99,

Please check this thread.

Best regards,
Abdallah
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abouassi
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Moderator
315 Views
Registered: ‎03-25-2019

Hi @fpga_newbee99,

Please check this thread.

Best regards,
Abdallah
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