12-21-2017 08:24 PM
I have two Zynq 7000 devices using Aurora 8B10B and AXI Chip2Chip with Vivado 2016.4 (Can't use a newer version). Both FPGA designs use IP Integrator to instantiate the Aurora and AXI Chip2Chip blocks. One FPGA is obviously the AXI Chip2Chip Master and one is the AXI Chip2Chip Slave. They have matching config parameters other than the ones that are greyed out on the Master one. This link is duplicated 4 times on a customer high speed CCA. The 4 Master sides are all in one Zynq 7000 FPGA. The 4 Slave sides are each in independent Zynq7000 FPGAs, which are the same identical FPGA design programmed into all 4 Zynq 7000 slave sides. The same reference clock is provided to all 5 FPGAs. I have two issues that are presenting:
1) Most of the time all 4 links come up fine and the AXI Chip2Chip blocks indicate link status = '1'. There are some times when a few of the links indicate link status = '0' and link config error = '1'. It is not always the same links that fail. Sometimes one or two of them fail and sometimes 2 or 3 fail. From documentation, config error is due to "auto negotiation" not settling on the same paremeters between Master and Slave. All the Masters and Slaves are setup the same and since some of the time they all come up fine, this makes no sense. Any suggestions?
2) Sometimes, when link status = '1', the address provided on to the Master AXI Chip2Chip block comes out corrupt on the Slave AXI Chip2Chip block. When it happens it always happens over and over and over until a reset/power cycle. This does not always happen and most of the time things work just fine. Any suggestions?
Thanks in advance for any help you many provide.
12-21-2017 09:19 PM
12-21-2017 09:45 PM
Thanks for the quick reply. I will try that suggestion. Seems like a long shot, but maybe it will work. Any other suggestions will be greatly appreciated.
12-25-2017 01:05 AM
Could you confirm like clock jitter ?
For example, Display Port, which is used GTX to send/receive high speed serial signal, has a constraint of spread spectrum as clock jitter.
I guess it is similar concept.
So, could you confirm like clock jitter ?
07-29-2019 05:53 AM
Hello, I have met the same problem above, channel up is ok, lane up is ok on both master and slave side, occasionally link status is nok, at the same time, there is a config error. Reset can resolve this. I designed six chip2chip lane, only two of them has this problem, the other four is always OK.