03-07-2018 08:11 AM - edited 03-08-2018 07:07 AM
I am trying to understand the way the CAN peripheral module (CAN0) works on the XC7Z010-1CLG225C. It is actually part of the board Zynqberry TE 0726-02, but as far as it concerns only the chip, I do not think it is relevant.
I created in Vivado (2017.4) a project to configure the hardware, and exported it to SDK, and then imported an example available from the BSP documentation.
In the IP core configuration for the Zynq7 PS, the clock config for the CAN module shows three clocks (CANCLK, CAN0 MIOCLK and CAN1 MIOCLK). I have not found any valuable info about the meaning of these clocks, but as far as I understand, the one that is used is the CANCLK (which in the config appears as being taken from the IOPLL, with a frequency of 100MHz - The other CAN# MIOCLK appear as External, with an "actual" frequency of 23.8095Mhz). Which one would be the important here?
In the code in SDK, I modified the defines from any example (There was a post in the forums where someone asked how the values of the examples were obtained, as they didn't match with the formulas in UG585, but the only answer was a modified equation, without much explanation), and changed the loopback mode to Normal mode (as in my hardware I assigned the tx and rx pins to MIO pins, where I attached an adequate CAN transceiver, also attached to a CAN Analyzer). I used a recommended web calculator (http://www.bittiming.can-wiki.info/) with Clock Rate=100MHz, Sample Point=87.5%, SJW=1, Bit Rate=500kbps, and the values were Prescaler=25, SEG1=6, SEG2=1, numTQ=8. But with those values, I haven't been able to get any communication at all. I am pretty sure that it is a bit rate problem, given that when I run the examples in Loopback mode, everything seems to work.
What could I be missing, or where can I find more information about the CAN peripheral in this chip?
Thanks in advance
03-08-2018 07:12 AM
Works in loopback?
Does that board bring out the CAN interface pins? What did you connect it to?
All clocks are needed.
03-08-2018 08:01 AM
03-09-2018 06:55 AM
Looks like you have all the right tools,
So it is a matter of selecting all the right options, connecting up all the clocks.
Perhaps someone else can comment here. I have never used a CAN interface before.
06-25-2018 01:42 AM
Yes, I did solve the problem. Perhaps it is not the more professional solution, but as far as the goal of the project, worked for me:
The clock frequency selected in the config of the Zynq PS was by default at 100MHz. As mentioned, there is a website that helps to calculate the config parameters of common CAN implementations (including XCAN for Xilinx). http://www.bittiming.can-wiki.info/
From them, I recognized that they even show when the calculated config produce exactly 16 Time Quanta. With 100MHz and a CAN baud rate of 500 kbps, it was not possible. I modified the freq to 80MHz, and used the values recommended for the calculator, and then worked.