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zynq_Learner
Newbie
Newbie
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Registered: ‎03-05-2021

Zynq-7000 Verification IP S_AXI_HP0 never assert RVALID(The version of vivado is 2018.3)

I'm using the Zynq-7000 Verification IP and my vivado’version is 2018.3.There is a serious problem which is mentioned below. 

The documentation of ZYNQ VIP:

https://www.xilinx.com/support/documentation/ip_documentation/processing_system7_vip/v1_0/ds940-zynq-vip.pdf

 

IPs I used are below:

  1. Processing System(ZYNQ-7000 VIP)
  2. Processor system reset
  3. Two AXI interconnect
  4. My user_defined IP(AXI Control_v1_0_0)

The figure of my block design is shown below.

 

I have used write_data and read_data APIs to perform write and read transfer of AXI_GP_Master Port of ZYNQ VIP, and it works fine. However, the S_AXI_HP0 doesn't assert RVALID after I used pre_load_mem API to load the OCM/DDR memory model and trigger my user-defined IP by M_AXI_GP Port. My user-defined IP asserts ARRVALID and ZYNQ VIP have responses (ARREADY = 0, the simulation diagram is shown below). After that, the RVALID signal is never asserted.The yellow bus is the path from my user-defined ip(axi master port) to zynq vip(axi slave port).

D-AXI Problem.JPG

 

block design3.jpg

 

My user-defined IP have worked fine on the zynq-7000 board-level verification before I use this ZYNQ VIP to run the behavioral simulation.So I don’t know why the read channel of S_AXI_HP0 can’t work on the ZYNQ 7000 VIP.

My testbench file in this project is attached below.I will be very grateful if you can help me.

 

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