I have used write_data and read_data APIs to perform write and read transfer of AXI_GP_Master Port of ZYNQ VIP, and it works fine. However, the S_AXI_HP0 doesn't assert RVALID after I used pre_load_mem API to load the OCM/DDR memory model and trigger my user-defined IP by M_AXI_GP Port. My user-defined IP asserts ARRVALID and ZYNQ VIP have responses (ARREADY = 0, the simulation diagram is shown below). After that, the RVALID signal is never asserted.The yellow bus is the path from my user-defined ip(axi master port) to zynq vip(axi slave port).
My user-defined IP have worked fine on the zynq-7000 board-level verification before I use this ZYNQ VIP to run the behavioral simulation.So I don’t know why the read channel of S_AXI_HP0 can’t work on the ZYNQ 7000 VIP.
My testbench file in this project is attached below.I will be very grateful if you can help me.