04-07-2014 06:21 AM
we are writing two applications that shall run on both cores of Zynq (we're testing them on the ZC702 evaluation board); the applications need to be synchronized, so we've written lock/unlock routines using ldrex/strex ARM instructions (following directions in "ARM Synchronization Primitives" article), but something weird happens: while core0 quietly locks and unlocks, in core1 strex always fails; we tried using an address in OCM and one in RAM but nothing changes: strex always returns 1. I can't figure out where the problem is: I suspect something's wrong with memory attributes (they have been set to 0x14de2) but I'm not really sure... Can somebody lend a hand?
This is the code we use for lock/unlock:
lock_mutex: /* lock_mutex */ dmb ish /* Declare for use from C as extern void lock_mutex(void * mutex) */ ldr r1, =locked _lbl1: ldrex r2, [r0] cmp r2, r1 // test if mutex is locked or unlocked beq _lbl2 // if locked - wait for it to be released, from _lbl2 strexne r2, r1, [r0] // not locked, attempt to lock it cmpne r2, #1 // check if store-exclusive failed beq _lbl1 // failed - retry from _lbl1 // lock acquired dmb // required before accessing protected resource bx lr _lbl2: // take appropriate action while waiting for mutex to become unlocked wfe b _lbl1 // retry from _lbl1 .global unlock_mutex unlock_mutex: // unlock_mutex // Declare for use from C as extern void unlock_mutex(void * mutex) ldr r1, =unlocked dmb // required before releasing protected resource str r1, [r0] // unlock mutex clrex dsb sev bx lr
Thank you very much!
04-07-2014 08:55 AM
04-07-2014 08:55 AM
04-11-2014 07:47 AM
I do have the same issue and already had a look at the suggested post but not sure I interpreted it correctly. The phrasing is a bit confused...
How did you finally configure your memory attributes and the L2 Auxiliary Control Register ? Can you provide the values you used in your working setup ?
04-16-2014 06:40 AM
Hi, after an initial moment of enthusiasm we ran into problems that seemed to be solved with a weird memory attributes setting... I explained the situation in the same discussion cited above.