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kkoorndyk
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Registered: ‎02-12-2009

Zynq BFM Simulation and DDR memory model

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I have the Zynq BFM simulating to verify a custom AXI3 master pushing data into DDR from the PL through HP0.

 

The simulation cycles all appear to look correct and are working fine on at the Zynq BFM inst interface.  However, when attempting to dump the contents of the DDR memory model, nothing happens.  An empty file is created.

 

I started digging into the BFM code to trace the data path through the HP0 interface... but it doesn't appear to be tied to anything!

 

processing_system7_bfm_v2_0_processing_system7_bfm.v, searching for S_AXI_HP0_WDATA only shows it as an input but it isn't tied to anything.  

 

Tracing back from processing_system7_bfm_v2_0_ddrc.v where the memory model is instantiated, the data flows through the processing_system7_bfm_v2_0_interconnect_model.v.  Looking at the instantiation of the ICM, I find the following:

 

/* HP Slave ports access */
.wr_ack_ddr_hp0(net_wr_ack_ddr_hp0),
.wr_ack_ocm_hp0(net_wr_ack_ocm_hp0),
.wr_data_hp0(net_wr_data_hp0),
.wr_addr_hp0(net_wr_addr_hp0),
.wr_bytes_hp0(net_wr_bytes_hp0),
.wr_dv_ddr_hp0(net_wr_dv_ddr_hp0),
.wr_dv_ocm_hp0(net_wr_dv_ocm_hp0),

....

 

So the ports are tied to unused wires that don't go anywhere.  Am I missing something?  Did I miss some configuration step in generating the BFMs?

 

 

 

DornerWorks
https://goo.gl/LNexn5



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kkoorndyk
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Registered: ‎02-12-2009

Actually, it is working.  The files just aren't updated on the disk until after the simulation completes or the tool is closed.

 

DornerWorks
https://goo.gl/LNexn5



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muzaffer
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Registered: ‎03-31-2012

Unfortunately most of the connectivity is handled through included modules. Check out processing_system7_bfm_v2_0_afi_slave.v. Grep is your friend. 

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kkoorndyk
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Registered: ‎02-12-2009

ah, I missed the includes at the bottom of the top level BFM.  I'm seeing the data path now and I am able to trace it down to the DDRC.  However, the peek_mem_to_file() task in the processing_system7_bfm_v2_0_sparce_mem.v file doesn't seem to be working.

 

DornerWorks
https://goo.gl/LNexn5



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kkoorndyk
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Registered: ‎02-12-2009

Actually, it is working.  The files just aren't updated on the disk until after the simulation completes or the tool is closed.

 

DornerWorks
https://goo.gl/LNexn5



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akselvaraj22
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Registered: ‎07-01-2015

In PL i have custom axi4 master interface and connect to HP ports and which then stores data in PS DDR3 Memory.

Then same port is used to read the data from DDR3.

 

I have to simulate the design which has PL+PS, Please let me know how can i proceed?

 

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muzaffer
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Registered: ‎03-31-2012
currently there is no integrated PS simulation option. There is only zynq bus functional model which emulates the interconnect and memory etc. This is an extra license item. Or you can be brave and try this: http://blog.dspia.com/2015/08/05/open-source-axi3-bus-functional-model-bfm/
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