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Visitor
Visitor
4,610 Views
Registered: ‎06-20-2013

Zynq DCM error message in MAP

I'm using a MicroZed board with carrier card with an external clock going to a DCM. The Zynq part is: XC7Z010-1CLG400C. I used coregen to generate the DCM. During the MAP stage in PlanAhead, I get the following error:

ERROR:PhysDesignRules:2369 - Issue with pin connections and/or configuration on
   block:<XciterMicroZed_i/xcitermicrozed_0/xcitermicrozed_0/USER_LOGIC_I/xciter
   1/DCM_IIS_10_4MHZ/mmcm_adv_inst>:<MMCME2_ADV_MMCME2_ADV>.  The MMCME2_ADV
   with CLKINSEL tied high requires the CLKIN1 pin to be active.
ERROR:Pack:1642 - Errors in physical DRC.

 

Here's the DCM code from coregen:

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "DCM_IIS,clk_wiz_v3_6,{component_name=DCM_IIS,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=96.153,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module DCM_IIS
 (// Clock in ports
  input         CLK_IN1,
  // Clock out ports
  output        CLK_OUT1,
  // Status and control signals
  input         RESET,
  output        LOCKED
 );

  // Input buffering
  //------------------------------------
  IBUFG clkin1_buf
   (.O (clkin1),
    .I (CLK_IN1));

  // Clocking primitive
  //------------------------------------
  // Instantiation of the MMCM primitive
  //    * Unused inputs are tied off
  //    * Unused outputs are labeled unused
  wire [15:0] do_unused;
  wire        drdy_unused;
  wire        psdone_unused;
  wire        clkfbout;
  wire        clkfbout_buf;
  wire        clkfboutb_unused;
  wire        clkout0b_unused;
  wire        clkout1_unused;
  wire        clkout1b_unused;
  wire        clkout2_unused;
  wire        clkout2b_unused;
  wire        clkout3_unused;
  wire        clkout3b_unused;
  wire        clkout4_unused;
  wire        clkout5_unused;
  wire        clkout6_unused;
  wire        clkfbstopped_unused;
  wire        clkinstopped_unused;

  MMCME2_ADV
  #(.BANDWIDTH            ("OPTIMIZED"),
    .CLKOUT4_CASCADE      ("FALSE"),
    .COMPENSATION         ("ZHOLD"),
    .STARTUP_WAIT         ("FALSE"),
    .DIVCLK_DIVIDE        (1),
    .CLKFBOUT_MULT_F      (64.000),
    .CLKFBOUT_PHASE       (0.000),
    .CLKFBOUT_USE_FINE_PS ("FALSE"),
    .CLKOUT0_DIVIDE_F     (16.000),
    .CLKOUT0_PHASE        (0.000),
    .CLKOUT0_DUTY_CYCLE   (0.500),
    .CLKOUT0_USE_FINE_PS  ("FALSE"),
    .CLKIN1_PERIOD        (96.153),
    .REF_JITTER1          (0.010))
  mmcm_adv_inst
    // Output clocks
   (.CLKFBOUT            (clkfbout),
    .CLKFBOUTB           (clkfboutb_unused),
    .CLKOUT0             (clkout0),
    .CLKOUT0B            (clkout0b_unused),
    .CLKOUT1             (clkout1_unused),
    .CLKOUT1B            (clkout1b_unused),
    .CLKOUT2             (clkout2_unused),
    .CLKOUT2B            (clkout2b_unused),
    .CLKOUT3             (clkout3_unused),
    .CLKOUT3B            (clkout3b_unused),
    .CLKOUT4             (clkout4_unused),
    .CLKOUT5             (clkout5_unused),
    .CLKOUT6             (clkout6_unused),
     // Input clock control
    .CLKFBIN             (clkfbout_buf),
    .CLKIN1              (clkin1),
    .CLKIN2              (1'b0),
     // Tied to always select the primary input clock
    .CLKINSEL            (1'b1),
    // Ports for dynamic reconfiguration
    .DADDR               (7'h0),
    .DCLK                (1'b0),
    .DEN                 (1'b0),
    .DI                  (16'h0),
    .DO                  (do_unused),
    .DRDY                (drdy_unused),
    .DWE                 (1'b0),
    // Ports for dynamic phase shift
    .PSCLK               (1'b0),
    .PSEN                (1'b0),
    .PSINCDEC            (1'b0),
    .PSDONE              (psdone_unused),
    // Other control and status signals
    .LOCKED              (LOCKED),
    .CLKINSTOPPED        (clkinstopped_unused),
    .CLKFBSTOPPED        (clkfbstopped_unused),
    .PWRDWN              (1'b0),
    .RST                 (RESET));

  // Output buffering
  //-----------------------------------
  BUFG clkf_buf
   (.O (clkfbout_buf),
    .I (clkfbout));

  BUFG clkout1_buf
   (.O   (CLK_OUT1),
    .I   (clkout0));
endmodule

 

My UCF file contains:

NET xcitermicrozed_0_CLK_IIS_pin LOC = N18 | IOSTANDARD=LVCMOS33 ;

NET "xcitermicrozed_0_CLK_IIS_pin" TNM_NET = "CLK_IIS";
TIMESPEC TS_CLK_IIS = PERIOD "CLK_IIS" 14.592 MHz HIGH 50%;

 

The pin is a MRCC pin which is clock capable, I believe. I've tried SRCC pins and get the same error.

 

I'm running PlanAhead 14.6.

 

I can't figure out what I'm doing wrong. I've been through this process successfully using the Zynq702 board on an earlier project.

 

Any help? Thanks.

 

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3 Replies
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Xilinx Employee
Xilinx Employee
4,605 Views
Registered: ‎09-20-2012

Re: Zynq DCM error message in MAP

Hi,

 

Can you open synthesized design and check how this MMCM input pin is connected?

 

Can you post the schematic of the same?

 

I tried running the coregen code which you posted by locking CLKIN1 port to N18, I did not see any error.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Highlighted
Visitor
Visitor
4,595 Views
Registered: ‎06-20-2013

Re: Zynq DCM error message in MAP

I just opened the RTL Schematic view of the synthesized design and it appears the CLk_IIS input is grounded. I'm not sure how this occurred.
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Visitor
Visitor
4,592 Views
Registered: ‎06-20-2013

Re: Zynq DCM error message in MAP

Okay, I just figured it out. I forgot to do the "Make External" step in XPS on my pins. It's passing now.