Zynq EPP Ehernet MAC has internal DMA with desriptor rings for both rx and tx channels. And it looks nice for data transferring between core and system memory and vise versa.
But what if our application requires redirect raw ethernet frames to PL for rx channel and gather frames from PL for tx channel?
After brief look at TRM one of the solution is the following. For RX channel. Set up descriptor ring and rx buffers in system memory and allow Eth MAC DMA do it work. After that set up separate system DMA to transfer data between memory and AXI_GP (general purpose port). For TX channel. Set up data transferring from PL via AXI_HP (high performance post) to system memory. And then point Eth MAC DMA tx buffers to the same memory location.
Synchronization of such data flow looks not trivial! Also additional latency is not desirable.
Do we have any other solution of such problem? Any ideas?
Did you ever get a solution for this? We have similar issue where logic in PL is trying to send packets directly out of gige MAC. We donot want to incur the latency of going though AXI_HP to memory/cache and then rely on the processor to DMA data out of cache to gige MAC. is there way to setup MAC's internal DMA to fetch data directly from PL uusing AXI_GP?