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akkadhim1
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Registered: ‎06-20-2016

Zynq Frequency scaling

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Hi 

 

I'm trying to scale the CPU frequency to the lowest frequency 333333 kHz but I got the below error

cpu cpu0: failed to set clock rate: -16

 

My devicetree pcw.dtsi file has the following settings:

 

cpus {
		cpu@0 {
			operating-points = <666666 1000000 333333 1000000>;
		};
	};

 

 

and zynq-7000.dtsi file has the following:

 

cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			clocks = <&clkc 3>;
			clock-latency = <1000>;
			cpu0-supply = <&regulator_vccpint>;
			operating-points = <
				/* kHz    uV */
				666667  1000000
				333334  1000000
			>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			clocks = <&clkc 3>;
		};
	};

 

 

is this the reason behind that error  (different frequencies) or there is another issue?

I configured the kernel and the governor is the userspace as below:

 

# cat scaling_governor 
userspace

also can I add another operating frequency like 222222 KHz? and do I need to change just the devicetree file?

 

My current available frequencies:

 

# cat scaling_available_frequencies 
333333 666666

Regards.

 

 

 

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austin
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Registered: ‎02-27-2008

ds187,

 

Table 21: PS PLL Switching Characteristics,

 

FPSPLL_MIN PLL minimum output frequency 780 MHz.

 

There is hardware to consider.  Not every number is allowed.  Read the data sheet.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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austin
Scholar
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Registered: ‎02-27-2008

ds187,

 

Table 21: PS PLL Switching Characteristics,

 

FPSPLL_MIN PLL minimum output frequency 780 MHz.

 

There is hardware to consider.  Not every number is allowed.  Read the data sheet.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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akkadhim1
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Registered: ‎06-20-2016

Thank you @austin

 

I got the idea, I have to activate the PLL bypass to select the 333333 frequency, as explained in the below link.

http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Low+Power+Techniques+part+5+-+Linux+Application+Control+of+Processing+System+-+Frequency+Scaling+%26+More+Tech+Tip

 

About the operating frequencies, I checked the document you mentioned and in table 17, it is possible to select the frequency 222 MHz, so how can I include this frequency? just add it in the devicetree?

 

Regards.

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vibishna
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Registered: ‎05-03-2016

Hi,

 

I hope setting the cpu governor to userspace helped to avoid the "cpu0: failed to set clock rate: -16" error

You can definitely add the additional frequency in your clock tree:

cpus {
         cpu@0 {
                         operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240 0x3640f 0xf4240>; // 666667 1000000  333334 1000000 222223 1000000
};

};

 

It will be listed in the "cat scaling_available_frequencies"

But for some reason it is given in one of the Xilinx forum that the lowest frequency of 222Mhz is not reachable in default configuration. 

 

I am trying to figure out why is the lowest frequency not reachable!

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akkadhim1
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Registered: ‎06-20-2016
Hi @vibshna

Thank you for your response.

Yes I read that also, but I think if you followed the method in this application you can do that:

http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Low+Power+Techniques+part+5+-+Linux+Application+Control+of+Processing+System+-+Frequency+Scaling+%26+More+Tech+Tip

Regards.
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vibishna
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Registered: ‎05-03-2016

Hi @akkadhim1

 

Can you tell me if you were able to fix the problem of  setting to 222Mhz? If yes, please tell me exactly which step solved the problem!

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akkadhim1
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Registered: ‎06-20-2016

hi @vibishna

unfortunately, I haven't solved the problem, and because my project deadline was due,  I simply stopped working on it. I'll let you know if I get around the project again.

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