12-12-2012 10:34 AM
Hi. I have created a custom AXI Burst Master peripheral (via XPS) and connected it to the HP0 Slave port on the Zynq PS. I am testing on a Zedboard, and am finding that during an AXI Burst Read, the HP0 AXI port is only returning every other 32-bit word during transactions.
For testing, I am using a baremetal application using cacheFlush to load the DDR with values.
Starting at DDR address 0x10000000, the application loads an incrementing 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, etc at each byte of memory.
When I request an 16 word AXI Burst Master Read from my 32-bit custom peripheral, the data only toggles every other clock, and only returns every other word.
So,the peripheral receives:
0x03020100 followed by 0x0B0A0908, followed by 13121110.
However, I would have expected to receive:
0x03020100 followed by 0x07060504, followed by 0x0B0A0908, followed by 0x0F0E0D0C.
See attached Chipscope AXI trace.
Any thoughts on what I am missing? I suspect it is an AXI width mismatch. That said, I have double-checked the AXI peripheral setup, AXI interconnect setup, and HP0 port are all setup for 32 bit width.
I also double-checked the AXI clocks to confirm that they are all driven by the same 100MHz clock. (It almost looks like the HP0 port was running on a 50MHz clock).
12-12-2012 03:50 PM
That screen shot is a bit though to read. Can you post again (maybe as an attachment), showing the entire bus.
Also, it may be helpful if you can post your .mhs as well.
Are you keeping an eye on your keep/strb signals? How about your response signals? Any errors there?
11-05-2020 02:58 PM - edited 11-05-2020 02:59 PM
I've encountered the same exact problem in my design on 7020 (Pynq Z2 board, Vivado 19.1) and it took me a while to figure it out.
In case of anyone having similar problem in future - the solution was to change AFI_RDCHAN_CTRL (0xF8008000) bit 0 from '0' to '1'.