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Azuldev
Visitor
Visitor
768 Views
Registered: ‎06-16-2020

Zynq IRQ0 using PL_PS

My Problem

I am trying to fire a PL_PS interrupt created using Vivado 2018.3 to target ARM-Cortex53

I've attached the IP settings and the block diagram as jpegs.

The following  code was my attempt with no success.
I summarized as needing to take 10 steps to work with IRQs.

My Question....am I missing any steps ?

During the test sequence I toggle the input signal from low to high using Vivado and monitoring with an ILA. (But nothing happens)


#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "xscugic.h"
#include "xparameters.h"

XScuGic IntcInstance;                  //STEP 1      Instance
XScuGic_Config *IntcConfig;            //STEP 2      Pointer

 

// ------------------------------------------------------------ Function Called During trigger-------------------------------------------//

static void my_int_function(){

//disable interrupt

XScuGic_Disable(&IntcInstance,XPAR_FABRIC_INT_IN_INTR); 

print("Hello World from handle \n\r"); 

XScuGic_Enable(&IntcInstance,XPAR_FABRIC_INT_IN_INTR);

}

 

//---------------------------------------------------Start of Main--------------------------------------------------------//

int main()

{

init_platform();

u32 status;


IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_0_DEVICE_ID);           //STEP 3    LookUp  config XPAR variable came from xparamaters.h

 status = XScuGic_CfgInitialize(&IntcInstance,IntcConfig,IntcConfig->CpuBaseAddress);        //STEP 4  Assign to Cpu

if(status != XST_SUCCESS){

 xil_printf("Interrupt controller initialization failed...");

return -1;

}

XScuGic_SetPriorityTriggerType(&IntcInstance,XPAR_FABRIC_INT_IN_INTR,0x00,3);   //STEP 5     "3" for Rising Edge Trigger  

// XPAR_FABRIC_INT_IN_INTR is 121U from xparamaters.h

 status =XScuGic_Connect(&IntcInstance,XPAR_FABRIC_INT_IN_INTR,(Xil_InterruptHandler)my_int_function,0);      //STEP 6  Connect to my function

 

if(status != XST_SUCCESS){

 xil_printf("Connection Failed");

return -1;

}

XScuGic_Enable(&IntcInstance,XPAR_FABRIC_INT_IN_INTR);                //STEP 7  enable trigger

Xil_ExceptionInit();          //STEP 8   Required Inits ? Maybe   

Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler)XScuGic_InterruptHandler,(void*)&IntcInstance);    //STEP 9 required

Xil_ExceptionEnable();           //STEP 10 required

 print("Hello World\n\r");

while(1){

}

cleanup_platform();

return 0;

}

 

 

 

set_up.PNG
block diagram.PNG
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6 Replies
sabankocal
Voyager
Voyager
738 Views
Registered: ‎08-02-2019

Hi  @Azuldev ,

I'm using interrupts on both of Petalinux and Bare Metal side with Vivado 2018.2. My board is ZC702, not ultrascale.

I read a lot of common mistakes about interrupts in this forum. I can say you some of them :

  • Did you checked your interrupt input really fired on Vivado by using ILA. I mean pl_ps_irq0[7:0] bus.
  • Most of the users make interrupt number mistake. They write intr. numbers as they think. It seems you are doing it properly. You are getting it from xparameters.h. you need to be sure about your bsp project on SDK. After new bit generation sometimes it can not update itself and you need to say "Re-generate BSP sources". If it leaves old, it can corrupt everything.
  • Abou CPU selection a lot of people make mistake. You need to be carefull about your CPU's actual number.
  • To test your interrupt you can debug Xilinx SDK easily.

I removed unrelated parts on my BareMetal code and sharing with you. It uses Xilinx's Xapp1078 as base.

You can compare it with yours. I know, Ultrascale is a little bit different, but I hope it helps.

Saban

 

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sabankocal
Voyager
Voyager
694 Views
Registered: ‎08-02-2019

Hi @Azuldev,

I 'm sharing my code as an example.

Saban

 

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abhinayp
Xilinx Employee
Xilinx Employee
576 Views
Registered: ‎07-12-2018

Hi @Azuldev 

Looks you have connected external interrupts to the PL_PS_IRQ port. Did you check if the bus is defined as intr type in the port settings? 

There is no signal on the ILA, but what about the external line, Is signal asserted till the external port?

Code looks fine and also xparameters.h

Best Regards
Abhinay PS
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pedro_uno
Advisor
Advisor
571 Views
Registered: ‎02-12-2013

I have been messing with that too.  You can find a working example with fpga and vitis bare metal project here.

    https://github.com/hdlguy/freertos_test/tree/master/zed_scugic

You might find something useful.

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DSP in hardware and software
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pedro_uno
Advisor
Advisor
570 Views
Registered: ‎02-12-2013

I think you need a "concat" block in front of the pl_ps interrupt inputs.  You need that even if you are not concatenating busses.

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DSP in hardware and software
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pedro_uno
Advisor
Advisor
558 Views
Registered: ‎02-12-2013

I made a related post.

https://forums.xilinx.com/t5/Embedded-Development-Tools/AXI-Interrupt-Controller-under-FreeRTOS/m-p/1130403#M54462
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DSP in hardware and software
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