06-16-2020 12:52 PM
My Problem
I am trying to fire a PL_PS interrupt created using Vivado 2018.3 to target ARM-Cortex53
I've attached the IP settings and the block diagram as jpegs.
The following code was my attempt with no success.
I summarized as needing to take 10 steps to work with IRQs.
My Question....am I missing any steps ?
During the test sequence I toggle the input signal from low to high using Vivado and monitoring with an ILA. (But nothing happens)
#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "xscugic.h"
#include "xparameters.h"
XScuGic IntcInstance; //STEP 1 Instance
XScuGic_Config *IntcConfig; //STEP 2 Pointer
// ------------------------------------------------------------ Function Called During trigger-------------------------------------------//
static void my_int_function(){
//disable interrupt
XScuGic_Disable(&IntcInstance,XPAR_FABRIC_INT_IN_INTR);
print("Hello World from handle \n\r");
XScuGic_Enable(&IntcInstance,XPAR_FABRIC_INT_IN_INTR);
}
//---------------------------------------------------Start of Main--------------------------------------------------------//
int main()
{
init_platform();
u32 status;
IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_0_DEVICE_ID); //STEP 3 LookUp config XPAR variable came from xparamaters.h
status = XScuGic_CfgInitialize(&IntcInstance,IntcConfig,IntcConfig->CpuBaseAddress); //STEP 4 Assign to Cpu
if(status != XST_SUCCESS){
xil_printf("Interrupt controller initialization failed...");
return -1;
}
XScuGic_SetPriorityTriggerType(&IntcInstance,XPAR_FABRIC_INT_IN_INTR,0x00,3); //STEP 5 "3" for Rising Edge Trigger
// XPAR_FABRIC_INT_IN_INTR is 121U from xparamaters.h
status =XScuGic_Connect(&IntcInstance,XPAR_FABRIC_INT_IN_INTR,(Xil_InterruptHandler)my_int_function,0); //STEP 6 Connect to my function
if(status != XST_SUCCESS){
xil_printf("Connection Failed");
return -1;
}
XScuGic_Enable(&IntcInstance,XPAR_FABRIC_INT_IN_INTR); //STEP 7 enable trigger
Xil_ExceptionInit(); //STEP 8 Required Inits ? Maybe
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler)XScuGic_InterruptHandler,(void*)&IntcInstance); //STEP 9 required
Xil_ExceptionEnable(); //STEP 10 required
print("Hello World\n\r");
while(1){
}
cleanup_platform();
return 0;
}
06-16-2020 04:53 PM
Hi @Azuldev ,
I'm using interrupts on both of Petalinux and Bare Metal side with Vivado 2018.2. My board is ZC702, not ultrascale.
I read a lot of common mistakes about interrupts in this forum. I can say you some of them :
I removed unrelated parts on my BareMetal code and sharing with you. It uses Xilinx's Xapp1078 as base.
You can compare it with yours. I know, Ultrascale is a little bit different, but I hope it helps.
Saban
<------------------------------------------------------------------------------>
if(solves_problem) mark_as_solution <= 1 else if(helpful) Kudo <= Kudo + 1
06-17-2020 02:22 AM - edited 06-24-2020 09:09 AM
Hi @Azuldev,
I 'm sharing my code as an example.
Saban
07-21-2020 08:05 AM
Hi @Azuldev
Looks you have connected external interrupts to the PL_PS_IRQ port. Did you check if the bus is defined as intr type in the port settings?
There is no signal on the ILA, but what about the external line, Is signal asserted till the external port?
Code looks fine and also xparameters.h
07-21-2020 08:15 AM
I have been messing with that too. You can find a working example with fpga and vitis bare metal project here.
https://github.com/hdlguy/freertos_test/tree/master/zed_scugic
You might find something useful.
07-21-2020 08:17 AM
I think you need a "concat" block in front of the pl_ps interrupt inputs. You need that even if you are not concatenating busses.
07-21-2020 08:38 AM