I'm working on zc702 compatible development board for my project.
For my board, a 1GB DDR Memory is mapped to 0x0000_0000 ~ 0x3fff_ffff as a default
and I have added 512 MB DDR Memory with the address range : 0x6000_0000 ~ 0x7fff_ffff.
(I used GP0 AXI port)
Since my goal is to inspect AXI-based memory transactions in PL area,
I ported xilinx-zynq-linux to my board with (UIMAGE_LOADADDR = 0x60008000) setting.
(And I modified dts for memory mapping)
With DS-5 debugging supprot, I found that my system failed to enable MMU.
In a linux kernel startup function __setup_mmu, kernel initialize page section entries with appropriate attributes.
Because my linux kernel is running on 0x60000000 ~ 0x70000000,
the page entries for the region has Cacheable(C) and Bufferable(B) attributes.
When I ported the linux at 0x20000000 ~ 0x30000000, these attributes did not make any problem.
But, for newly added memory region, Cortex-A9 could not enable MMU.
It makes error continuously with the instructions below.
mcr p15, 0, r0, c7, c5, 4 @ ISB mcr p15, 0, r0, c1, c0, 0 @ load control register
(pending here) mrc p15, 0, r0, c1, c0, 0 @ and read it back
I don't know what I shoud do for solving this problem.
Address mapping for PL cannot be used as instruction memory?
Or, can I make it possible with some settings in PS?
Did you ever figure out this problem? I'm running into similar issues and am curious how you solved the problem.