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barco2
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Adventurer
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Registered: ‎02-13-2009

Zynq MPSoC AXI HPC FPD slave interfaces: usage of saxi_gp*_wcount vs WREADY

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Hi,

when using the the AXI slave interfaces of the Zynq7000 PS, the TRM explicitly allowed/encouraged to ignore the WREADY signal when checking the FIFO fill level ports instead. See attached screenshot from the manual.

For the Zynq MPSoC the manual does not describe this possibility anymore, actually the FIFO status ports are not easily accessible anymore and have to be explicitely enabled with the parameter CONFIG.PSU__EN_AXI_STATUS_PORTS.

Is it still possible to use those status ports instead of the WREADY signal to allow for an optimized AXI interface design?

Regards
Martin

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zynq7000.png
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barco2
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Adventurer
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Registered: ‎02-13-2009

Since nobody could answer this here, I filed a SR and got the following answer:

Zynq MPSoC only have single FIFO connected accross the all S_AXI interfaces. In case of Zynq, each slave port has its own FIFO and the status signals. So Its not possible to use the status signals instead of WREADY in Zynq MPSoC devices.

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barco2
Adventurer
Adventurer
529 Views
Registered: ‎02-13-2009

Since nobody could answer this here, I filed a SR and got the following answer:

Zynq MPSoC only have single FIFO connected accross the all S_AXI interfaces. In case of Zynq, each slave port has its own FIFO and the status signals. So Its not possible to use the status signals instead of WREADY in Zynq MPSoC devices.

View solution in original post

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