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2,387 Views
Registered: ‎12-07-2016

Zynq MPSoC Axi read/write 32 bit

Hello,

 

I'm using on a Zynq Ultrascale+ device the AXI HPM0 LPD port for communications with my custom AXI IP cores.

The design is migrated from a Zynq7000 project. So my IP cores should working.

 

For example I want to read a 32 bit register over Linux (/dev/mem or kernel module ioread32).

If I read the register 0x0800000 then i see two AXI transaction on address 0x0800000 and 0x08000004 over chipscope. So the ioread32 reads 64 bit from the memory and ignores the higher 32 bit.

Is this a common behavior?

This would mean that my IP cores are not compatible between Zynq7000 and Zynq Ultrascale+. Because my register mapping is 32 bit (as recommended from Xilinx)

 

Unbenannt.PNG

 

Do I something wrong or is there a setting for 32 bit access?

 

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a_chami
Explorer
Explorer
2,363 Views
Registered: ‎04-12-2017

Check if this AR helps you

 

https://www.xilinx.com/support/answers/66295.html

Avi Chami MSc
FPGA Site
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bhoevding
Contributor
Contributor
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Registered: ‎05-02-2019

Hello @andreas.bachmaier 

I am currently experiencing a similar issue.

In my case the previous system which was utilized was developed for a Zynq-7000 System with a 32-Bit-Linux. I have migrated to the Zynq-MP (UltraZed) Platform and I am experiencing issues with interfacing between the PS and PL. Reading through your question I would like to know your opinion regarding this issue.

Is it possible to compile the Linux-Kernel-Module and the User Application with a 32-Bit Compiler, and would you recommend this?

The PL-IP-Core also works with 32-Bit Registers so I would really appreciate your recommendation / experience as to how to move further with this issue?

best regards,

Bjørn

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1,162 Views
Registered: ‎12-07-2016

Hello @bhoevding 

I didn't do any further research. I think the single read data width is set with the AXI interface configuration. See Zynq UltraScale+ MPSoC IP Core --> PS-PL Configuration --> Master Interface -> AXI HPMx LPD Data Width. If you set this value to 64 Bit, a single read transaction (ioread32) leads to two AXI transaction on your 32 Bit AXI interface after a SmartConnect or AXI Interconnect.

If you set the Data Width property to 32 Bit, you will be fine

 

I'm using the standard aarch64-linux-gnu-gcc Compiler. Petalinux supports only a 64-bit Kernel. So I think it's not possible to use a 32-bit Kernel module.

 

I would appreciate if you share your further experience...

 

Regards,

Andreas

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bhoevding
Contributor
Contributor
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Registered: ‎05-02-2019

Hello @andreas.bachmaier,

in the current state I am enforced to use a 128-bit ACP Port, since chache coherency is not maintained by the software.

I have begun to port my kernel module to 64-bit, since there seems to be no alternative. I can report back, once I have a better understanding and a working system.

Regards

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