The Zynq Ultrascale+ MPSoC parts have built-in AXI Performance Monitor (APM) blocks at various places within the PS interconnect. In the TRM (UG1085), Figure 15-1 shows the APMs color coded in yellow. There is a section in the TRM titled "AXI Performance Monitor Programming Model" that gives some information on how to interact with the builtin APM blocks. Other than that, I cannot find any documentation on these blocks.
Presumably, these built-in APMs are just instances of the Xilinx AXI Performance Monitor IP which can be used in the PL. However, I cannot find any information about the customization parameters used for these built-in instance. It seems like it should be possible to use the Xilinx APM Linux driver with the built-in instances, but more details are needed to properly setup the device tree.
Where can I find the details of the built-in APM blocks that are needed to configure the device tree?