11-03-2016 05:52 AM
We are working on moving a PL design using the AXI register interface on M_AXI_HPM0_LPD (setup to 64 bit) from Vivado/SDK 2016.2 to 2016.3. We are using a "standard" boot using the Xilinx FSBL (a new SDK FSBL project was made to ensure 2016.3 FSBL source) After 2016.3 the register read/writes to our PL design was semi working. I traced it down to the LPD_SLCR.axi_fs.dw_ss2_sel register was set to 128 bit instead 64 bit after boot. Got some hints from:
The Vivado 2016.3 generated psu_init.c was correct:
PSU_Mask_Write (LPD_SLCR_AFI_FS_OFFSET ,0x00000300U ,0x00000100U);
Which is 64 bit. But the registers reads 0x00000200 (128 bit)
I can see the above register write is moved into the psu_ps_pl_isolation_removal_data() compared to the 2016.2 generated code. I searched psu_init and all FSBL source - and psu_ps_pl_isolation_removal_data() is never called.
I tried to put a call to psu_ps_pl_isolation_removal_data() in i XFsbl_HookPsuInit() (xfsbl_hooks.c) - then it works.
Is there a bug in the psu_init() and/or FSBL? - or should the "user" call it?