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Voyager
Voyager
1,385 Views
Registered: ‎03-17-2011

Zynq MPSoC : custom PS DDR memory interface

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Hi,

 

I'm facing a problem configuring the interface for the PS DDR controller.

 actual_interface.png

It says actual interface is 1066 MHz but I need it to be 1200MHZ. I can't see how to change this parameter.

Do you have suggestions? I think it must be simple but I can't find any information related to that matter in pg201 for instance.

Thanks.

 

--Sébastien

 

--Sebastien
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Xilinx Employee
Xilinx Employee
1,303 Views
Registered: ‎05-14-2018

Re: Zynq MPSoC : custom PS DDR memory interface

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Hi @sebo

   Beside of what proposed by Gareth, you should also check the items under "Full Power Domain" of "advance clocks" in the tap "clock configuration"-->"output clocks". Someone could be also a bottleneck for running PS DDR4 controller at 1200MHz.  :)

   In my case, I changed the source of "TOPSW_MAIN" from DPLL to VPLL, then the real frequency of DDR4 controller become 1200MHz from the original 1067.

Good Lucky

Claude Li

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Moderator
Moderator
1,359 Views
Registered: ‎06-29-2011

Re: Zynq MPSoC : custom PS DDR memory interface

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Hi @sebo

CL/CWL as per JEDEC sheet has some recommendations with regard to clock frequencies and so from v2017.1 new DRCs were introduced based on the actual frequency of DDR from the PS tool, earlier it was based on requested frequency from DDR.

Changing GPU PLL to IO or VPLL will make sure that the requested frequency should come close to Actual. Basically it is required to offload the DDR PLL.

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Kind regards,
Gareth
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Voyager
Voyager
1,354 Views
Registered: ‎03-17-2011

Re: Zynq MPSoC : custom PS DDR memory interface

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Hi @garethc,

Thanks for you answer. I'm not sure I understand it all.

I tried to change PLL on settings down below. No changes...

actual_interface1.png

 

--Sebastien
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Moderator
Moderator
1,316 Views
Registered: ‎06-29-2011

Re: Zynq MPSoC : custom PS DDR memory interface

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Hi @sebo

Basically you need to change the GPU to IOPLL or VPLL and just have the DDR assigned to DPLL. This will resolve the issue.

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Don’t forget to reply, kudo, and accept as solution.
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Kind regards,
Gareth
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Xilinx Employee
Xilinx Employee
1,304 Views
Registered: ‎05-14-2018

Re: Zynq MPSoC : custom PS DDR memory interface

Jump to solution

Hi @sebo

   Beside of what proposed by Gareth, you should also check the items under "Full Power Domain" of "advance clocks" in the tap "clock configuration"-->"output clocks". Someone could be also a bottleneck for running PS DDR4 controller at 1200MHz.  :)

   In my case, I changed the source of "TOPSW_MAIN" from DPLL to VPLL, then the real frequency of DDR4 controller become 1200MHz from the original 1067.

Good Lucky

Claude Li

View solution in original post

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Voyager
Voyager
1,293 Views
Registered: ‎03-17-2011

Re: Zynq MPSoC : custom PS DDR memory interface

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Hi Claude,

 

Yes! That worked! this was the parameter I need to change.

Thanks for your help!

 

Regards,

 

Sébastien.

--Sebastien
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Contributor
Contributor
740 Views
Registered: ‎05-07-2018

Re: Zynq MPSoC : custom PS DDR memory interface

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The DDR clock frequency is based directly off of the indicated PLL, but the PLLs are typically based off of the PSS_REF_CLK (other options are avaialbe) and the associated multipliers and divisors.  Your PSS_REF_CLK input frequency (typically 20-60MHz) may prevent you from running your DDR at the frequency you want regardless of what PLL, multipliers and divisors you configure.

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