06-27-2019 01:22 PM
Can the PS-GTR support mixed operation, ie, can I employ 2 for a PCIe gen1 x2 link and the other two as SGMII..?
06-28-2019 12:35 AM
Hi @dje666 ,
Are you using enabling differenet GT lanes for each peripheral?
If yes, the can do it.
07-03-2019 01:33 AM
Yes, I expect to commit two GTR lanes to the PCIe interface and the remaining two GTR lanes to the SGMII interfaces.
Can I set this up in the MPSoC IPI block?