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kerjavec
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Registered: ‎06-12-2018

Zynq PL access to APB registers

Hello,

I am working with zynq ultrascale+ and would like to implement a design that would only use PL without any software on Zynq.

I would like to access PS:
- DDR
- gigabit ethernet controller (GEM)

I am reading [1], [2].

It seems that I can access DDR without any problem. While for GEM I will need to configure GEM registers [2] which can be accessed via APB slave interface.

The question is, can I access APB registers [2] via PL or not?

[1], page 361 suggests that there is a way to access "IOP units" via the following paths:
- S_AXI_LPD -> LPD Main switch -> LPD inbound -> IOP inbound -> apb -> IOP units
- S_AXI_HP0_FPD -> TBU3 -> FPD main switch -> LPD inbound -> LPD inbound -> IOP inbound -> APB -> IOP units

zynqIOPunitsAccess.JPG

Would appreciate if some would take his time and confirm that it is possible to configure [2] registers (GEM registers) via PL connection without the need of zynq software.

[1]: https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
[2]: https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

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anzejakos
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Registered: ‎06-13-2019

It is possible to access DDR and other registers, such as DDR ECC register from PL trough S_AXI_HP*, preferably "S_AXI_HP1_FPD" or "S_AXI_HP2_FPD" as they designed for higher throughput.

To do so:

1. Click on Zynq UltraScale+MPSOC IP

2. PS-PL Configuration/General/Address Fragmentation set "Upper LPS Slaves" to '1'. This adds base slave interface "HP1_UPPER_LPS_SLAVES" in Block design address editor 

3. Open Address editor and (auto) assign address to  "HP1_UPPER_LPS_SLAVES". You can also do the same for DDR, "HP1_DDR_LOW/HIGH"

4. Voila, addresses from 0xFE00_0000 to 0xFEFF_FFFF get accessible trough S_AXI_HP*_FPD

 

Regards

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