I am working with zynq ultrascale+ and would like to implement a design that would only use PL without any software on Zynq.
I would like to access PS: - DDR - gigabit ethernet controller (GEM)
I am reading , .
It seems that I can access DDR without any problem. While for GEM I will need to configure GEM registers  which can be accessed via APB slave interface.
The question is, can I access APB registers  via PL or not?
, page 361 suggests that there is a way to access "IOP units" via the following paths: - S_AXI_LPD -> LPD Main switch -> LPD inbound -> IOP inbound -> apb -> IOP units - S_AXI_HP0_FPD -> TBU3 -> FPD main switch -> LPD inbound -> LPD inbound -> IOP inbound -> APB -> IOP units
Would appreciate if some would take his time and confirm that it is possible to configure  registers (GEM registers) via PL connection without the need of zynq software.