Zynq PL to PS interrupts failed on 2015.4

[guinnesstrinker]

Hi all,

I have just updated a working Vivado/SDK 2015.2 design to 2015.4 and ran into a problem with PL to PS interrupts.

Yes, I followed instructions on

http://www.xilinx.com/support/answers/55703.html

http://www.xilinx.com/support/answers/58942.html

After exporting HW-description to SDK I found this inside xparameters.h:

2015.2:

/* Definitions for Fabric interrupts connected to ps7_scugic_0 */
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_FULL_INT_INTR 91
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_HALF_INT_INTR 90
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_EMPTY_INT_INTR 89
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_FULL_INTROUT_INTR 88
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_HALF_INTROUT_INTR 87
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_EMPTY_INTROUT_INTR 86
#define XPAR_FABRIC_AXI_UART16550_0_IP2INTC_IRPT_INTR 85

2015.4:

#define XPAR_FABRIC_AXI_UART16550_0_IP2INTC_IRPT_INTR 91
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_EMPTY_INTROUT_INTR 90
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_HALF_INTROUT_INTR 89
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_FULL_INTROUT_INTR 88
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_EMPTY_INT_INTR 87
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_HALF_INT_INTR 86
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_FULL_INT_INTR 85

As you can see the interrupt-sources are in reverse order.

As a result NO interrupts are generated as expected!!!

After defining an own declaration in my SDK-source file like xparameters.h in 2015.2 Interrupts are working.

Are there any patches available ?????

[guinnesstrinker]

Hi all,

I have just updated a working Vivado/SDK 2015.2 design to 2015.4 and ran into a problem with PL to PS interrupts.

Yes, I followed instructions on

http://www.xilinx.com/support/answers/55703.html

http://www.xilinx.com/support/answers/58942.html

After exporting HW-description to SDK I found this inside xparameters.h:

2015.2:

/* Definitions for Fabric interrupts connected to ps7_scugic_0 */
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_FULL_INT_INTR 91
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_HALF_INT_INTR 90
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_EMPTY_INT_INTR 89
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_FULL_INTROUT_INTR 88
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_HALF_INTROUT_INTR 87
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_EMPTY_INTROUT_INTR 86
#define XPAR_FABRIC_AXI_UART16550_0_IP2INTC_IRPT_INTR 85

2015.4:

#define XPAR_FABRIC_AXI_UART16550_0_IP2INTC_IRPT_INTR 91
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_EMPTY_INTROUT_INTR 90
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_HALF_INTROUT_INTR 89
#define XPAR_FABRIC_TRANSMITTER_0_FIFO_FULL_INTROUT_INTR 88
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_EMPTY_INT_INTR 87
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_HALF_INT_INTR 86
#define XPAR_FABRIC_RECEIVER_0_O_FIFO_FULL_INT_INTR 85

As you can see the interrupt-sources are in reverse order.

As a result NO interrupts are generated as expected!!!

After defining an own declaration in my SDK-source file like xparameters.h in 2015.2 Interrupts are working.

Are there any patches available ?????

[balkris]

check these links
https://forums.xilinx.com/t5/Embedded-Linux/How-to-use-fabric-interrupts-on-Zynq-with-Linux/td-p/635066
http://www.xilinx.com/support/answers/50572.html

[guinnesstrinker]

Sorry. This doesnt help.

I use StandAlone, no Linux (xparameters.h ist generated as source in BoardSupportPackage).

I use 2015.4 resp. 2015.2, no 2014.x or 2013.x.

The problem is that in 2015.4 transfer of HW-Description from Vivado to BSP in SDK has a bug.

[chillis]

I am having the same problem going from 2015.2 to 2016.2.

It appears that the problem still exists.

The IRQ_F2P interface on the processing_system7_0 says it should be in the order that 2015.2 creates, not the reversed order that 2016.2 creates.

[guinnesstrinker]

That`s good to hear. So we are two.

Hopefully there will be any response from Xilinx....

[danwwright]

Make that 3 of us.  I'm using petalinux 2016.2 and I see no interrupts to the arm coming from the peripherals in the FPGA fabric.  It HAD been working under the 3.17 kernel.

And I have checked the irq numbers in xparameters.h and I'm using the right ones.  Maybe this will get fixed in 2016.3?

[guinnesstrinker]

2016.3 is available. Give it a try.

[perbaecklund@scandidos]

The problem exists on 2016.3. Xilinx are aware of it, let's hope a fix is released in 2016.4

[guinnesstrinker]

Did someone try 2016.4?

[gaohuitian]

I encounter the same problem in 2016.2, is it fixed in the later vision?

[rakeshmg]

Can confirm that this issue is present in 2017.2

[rakeshmg]

For those of you who come here to check for a soltion,

refer to https://www.xilinx.com/support/documentation/ip_documentation/processing_system7/v5_5/pg082-processing-system7.pdf

Page 13 and 14.

The problem occurs when you upgrade a project. One fix can be to change your block design by deleting

CONFIG.PCW_IRQ_F2P_MODE {REVERSE}  line, (you can add DIRECT instead of REVERSE also I guess)

Rakesh