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Registered: ‎11-06-2016

Zynq PS to PL PCAP bitsream configuration

I'm facing some issues while trying to configure the PL side through PCAP from PS. I'm implementing this as a python script using the DS-5 debugger on a zc706 connected using a DSTREAM over JTAG.


The method I'm using is described on pages 221-222 in the TRM.

According to the steps on pages 221-222 I reach step 10. however, the PCFG_PROG_B bit is never set thus not indicating that the PL has been configured.


Full steps performed:

  1. reset system
  2. pause 500
  3. stop
  4. ps7_init
  5. TRM example procedure as mentioned pages 221-222
  6. flash SW binary
  7. debug


Something I have noticed while debugging this is that the WR_FIFO_LVL_INT bit seems to always be set in register DEVCFG_INT_STS. I'm not sure if this is related at all.


I have also tried to activate the PS-PL level shifter after the PL has been activated (something which is not mentioned in the TRM example).


Is there anything expected to be configured before I start the PS to PL configuration procedure that I'm missing here?


Apart from the aforementioned example in the TRM is there a better way of handling this, i.e configure the PL with a bitstream using a non XSDK (DS-5) environment?

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