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Visitor
Visitor
9,788 Views
Registered: ‎05-12-2015

Zynq SPI via EMIO problem

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Hi,

 

I've an SPI core from the PL routed out to the pins via EMIO. The bank I'm routing to is 3.3V, the SPI pins are configured as 3.3V and I've tied SS_In high as per the instructions in the TRM. I'm getting SPI traffic fine, but it's 1.8V levels not 3.3V levels. Other pins on the same banks are doing 3.3V, but the SPI pins aren't doing what I'd like them to do. 

 

Does anyone have any suggestions as to what I've got wrong? 

 

Thanks

 

Paul

 

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Moderator
Moderator
15,708 Views
Registered: ‎07-31-2012

Hi ,

 

Please refer to http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Zynq-connect-PS-SPI-peripheral-through-EMIO-with-external-device/m-p/600394#M7321 and see if it helps.

 

Regards

Praveen

 

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Moderator
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Registered: ‎07-31-2012

Hi ,

 

Please refer to http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Zynq-connect-PS-SPI-peripheral-through-EMIO-with-external-device/m-p/600394#M7321 and see if it helps.

 

Regards

Praveen

 

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Visitor
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Registered: ‎05-12-2015

Hi,

 

Thanks for the link Praveen, but sadly that doesn't help. The link shows pretty much where I'd already got to. 

 

I've the SPI connections fed out via EMIO to external pins, the constraints file set up and the I/O report verifies that the SPI outputs should be running at 3.3V. My logic analyser wasn't very happy with what was coming out (it was expecting 3.3v logic) so I looked at the signals on the scope. It's SPI, it's just that it's on the wrong voltage. The device it's going to be driving might be ok with the lower voltages, but I'd rather it was done right.

 

The bank I'm routing to the pins though is configured for 3.3v, and several of the other pins going out through that bank are 3.3v and they're right, what I don't understand is how it's just the SPI signals on the wrong level. 

 

Any suggestions most welcome

 

Paul

 

 

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Visitor
Visitor
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Registered: ‎05-12-2015

I've solved my problem and thought I'd better post again to close the issue off. The issues wasn't with the FPGA, but the connector where the SPI lines were comming off. CS# and SCLK were shorting making the 3v3 signals look like 1v8 signals. 

 

Paul

 

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Moderator
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Registered: ‎07-31-2012

Thanks for the update and quick reply.

 

Regards

Praveen


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Observer
Observer
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Registered: ‎01-22-2014

Hello

 

I knwo this is solved however, I just did a similar thing in my recent blog I have included the code as well at 

 

http://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-ish-Chronicles-Part-82-Simple/ba-p/620899

 

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