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devik
Visitor
Visitor
5,387 Views
Registered: ‎02-05-2010

Zynq Spread Spectrum Clocking

I can't find any info whether we can use SS modulated clock as PS_CLK input.

Anyone know whether PS PLLs can track SS and what their bandwidth is ?

 

thanks, Martin

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smarell
Community Manager
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Registered: ‎07-23-2012

I haven't see any mention of this anywhere. For me it looks like it is not recommended as it is not documented anywhere.
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movax
Explorer
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Registered: ‎11-09-2013

Found this on a Google search -- bumping to see if anyone looking here has used say a +/- 1.00% spread-spectrum 33.333MHz oscillator to drive PS_CLK.

 

The parts I'm looking at have shared footprints for SSC vs. non-SSC, but looking to save myself a little validation time / BOM swapping if possible...

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devik
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Registered: ‎02-05-2010

It is some time from my first post. I did some tests in meanwhile and can 

say that Zynq with LPDDR2 @ 400MHz, PSCLK from CDCE913 at 33MHz

works even with maximum spreading supported by CDCE.

I measured DDR clock with spectrum analyser and it was spreaded 

correctly.

Martin

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movax
Explorer
Explorer
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Registered: ‎11-09-2013

Thanks for the datapoint -- I think I'll start with a basic -1.00% or -0.50% SSC option, as not to push the frequency out-of-spec when multiplied up in a PLL. I have seen Ethernet and PCIe devices use SSC easily in the past, and the USB clock isn't sourced from the Zynq, so will see what ends up happening.

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devik
Visitor
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Registered: ‎02-05-2010

WRT Ethernet, I'm not sure about what you say. PHY chip needs rather

precise non spreaded clock. We ended up to feed ETH and USB phys

from fpga and routed non-spreaded clock into fpga for multiplication..

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anunesgu
Moderator
Moderator
1,083 Views
Registered: ‎02-09-2017

Just updating on this thread, according to this AR, The Zynq devices have not been characterized for spread spectrum clock inputs to the main PS clock.

 

https://www.xilinx.com/support/answers/66817.html

 

Thanks.

Andre Guerrero

Product Applications Engineer

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