05-05-2015 04:19 PM
I can't find any info whether we can use SS modulated clock as PS_CLK input.
Anyone know whether PS PLLs can track SS and what their bandwidth is ?
05-12-2015 03:28 AM
03-24-2016 12:48 PM
Found this on a Google search -- bumping to see if anyone looking here has used say a +/- 1.00% spread-spectrum 33.333MHz oscillator to drive PS_CLK.
The parts I'm looking at have shared footprints for SSC vs. non-SSC, but looking to save myself a little validation time / BOM swapping if possible...
03-24-2016 03:16 PM
It is some time from my first post. I did some tests in meanwhile and can
say that Zynq with LPDDR2 @ 400MHz, PSCLK from CDCE913 at 33MHz
works even with maximum spreading supported by CDCE.
I measured DDR clock with spectrum analyser and it was spreaded
03-31-2016 07:23 PM
Thanks for the datapoint -- I think I'll start with a basic -1.00% or -0.50% SSC option, as not to push the frequency out-of-spec when multiplied up in a PLL. I have seen Ethernet and PCIe devices use SSC easily in the past, and the USB clock isn't sourced from the Zynq, so will see what ends up happening.
04-01-2016 12:59 AM
WRT Ethernet, I'm not sure about what you say. PHY chip needs rather
precise non spreaded clock. We ended up to feed ETH and USB phys
from fpga and routed non-spreaded clock into fpga for multiplication..
06-14-2018 04:56 PM
Just updating on this thread, according to this AR, The Zynq devices have not been characterized for spread spectrum clock inputs to the main PS clock.