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Adventurer
Adventurer
7,989 Views
Registered: ‎04-07-2015

Zynq Standby mode

Hi,

 

I use a Zedboard and I would like put the zynq in a standby mode (page 110 : http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf) but I don't know how I can do this. I use Xilinx SDK for program Zynq.

 

Have you got any examples ?

 

Thanks

Jo

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Scholar
Scholar
7,979 Views
Registered: ‎11-09-2013

just do it, where is the problem?

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Adventurer
Adventurer
7,961 Views
Registered: ‎04-07-2015

Yes but how ?

 

What is the function in C for put the proceesor in standby mode ?

 

Jo

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Scholar
Scholar
7,956 Views
Registered: ‎11-09-2013

c is a standard for an formal language.

 

c knows nothing about zynq or standby, hence there is no function in c that does it.

 

you need to write it.

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Adventurer
Adventurer
7,952 Views
Registered: ‎04-07-2015

Yes I know but Xilinx SDK generate many librairies for using the zynq and it don't have a lib for do that ?

 

In the UG585 (page 110) it say that it is necessary to set some bits in the mpcore.SCU_CONTROL_REGISTER for put the zynq in standby mode but which bit and how ?

 

I am new user with Zynq and ARM processor, where I can find the description of differents registers in the ARM processor ?

 

Jo

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Scholar
Scholar
7,946 Views
Registered: ‎11-09-2013

read Zynq TRM it must be described there.

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Adventurer
Adventurer
7,941 Views
Registered: ‎04-07-2015

I follow this step :

 

Enter Sleep Mode

A CPU must execute the following steps to enter sleep mode from normal run mode:

1.Disable interrupts. Execute cpsid if.

2.Configure wake-up device.

3.Enable L2 cache dynamic clock gating. Set l2cpl310.reg15_power_ctrl[dynamic_clk_gating_en]=1.

4.Enable SCU standby mode. Set mpcore.SCU_CONTROL_REGISTER[SCU_standby_enable] = 1.

5.Enable topswitch clock stop. Set slcr.TOPSW_CLK_CTRL[CLK_DIS] = 1.

6.Enable Cortex-A9 dynamic clock gating. Set cp15.power_control_register[dynamic_clock_gating] =1.

7.Put the external DDR memory into self-refresh mode. Refer to section 10.9.6 DDR Power Reduction

8.Put the PLLs into bypass mode. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_BYPASS_FORCE] = 1.

9.Shut down the PLLs. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_PWRDWN] = 1.

10.Increase the clock divisor to slow down the CPU clock. Set slcr.ARM_CLK_CTRL[DIVISOR] = 0x3f

11.Execute the wfi instruction to enter WFI mode.

 

Exit Sleep Mode

To exit from sleep mode:

1.Restore CPU clock divisor setting. Set slcr.ARM_CLK_CTRL[DIVISOR] = <original value>.

2.Power on the PLLs. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_PWRDWN] = 0.

3.Wait for PLL power-on and lock. Wait for slcr.PLL_STATUS[{ARM, DDR, IO}_PLL_LOCK] == 1.

4.Disable PLL bypass mode. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_BYPASS_FORCE] = 0.

5.Disable L2 cache dynamic clock gating. Set l2cpl310.reg15_power_ctrl[dynamic_clk_gating_en]=0.

6.Disable SCU standby mode. Set mpcore.SCU_CONTROL_REGISTER[SCU_standby_enable] = 0.

7.Disable Interconnect clock stop. Set slcr.TOPSW_CLK_CTRL[CLK_DIS] = 0.

8.Disable Cortex-A9 dynamic clock gating. Set cp15.power_control_register[dynamic_clock_gating] =0.

9. Enable all required peripheral devices, including DDR controller clocks.

10.Re-enable and serve interrupts. Execute cpsie if.

 

In the Xilinx SDK, all registers are unknows.

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Visitor
Visitor
2,869 Views
Registered: ‎04-13-2017

YOU RIGHT


@jordanairbusds wrote:

I follow this step :

 

Enter Sleep Mode

A CPU must execute the following steps to enter sleep mode from normal run mode:

1.Disable interrupts. Execute cpsid if.

2.Configure wake-up device.

3.Enable L2 cache dynamic clock gating. Set l2cpl310.reg15_power_ctrl[dynamic_clk_gating_en]=1.

4.Enable SCU standby mode. Set mpcore.SCU_CONTROL_REGISTER[SCU_standby_enable] = 1.

5.Enable topswitch clock stop. Set slcr.TOPSW_CLK_CTRL[CLK_DIS] = 1.

6.Enable Cortex-A9 dynamic clock gating. Set cp15.power_control_register[dynamic_clock_gating] =1.

7.Put the external DDR memory into self-refresh mode. Refer to section 10.9.6 DDR Power Reduction

8.Put the PLLs into bypass mode. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_BYPASS_FORCE] = 1.

9.Shut down the PLLs. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_PWRDWN] = 1.

10.Increase the clock divisor to slow down the CPU clock. Set slcr.ARM_CLK_CTRL[DIVISOR] = 0x3f

11.Execute the wfi instruction to enter WFI mode.

 

Exit Sleep Mode

To exit from sleep mode:

1.Restore CPU clock divisor setting. Set slcr.ARM_CLK_CTRL[DIVISOR] = <original value>.

2.Power on the PLLs. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_PWRDWN] = 0.

3.Wait for PLL power-on and lock. Wait for slcr.PLL_STATUS[{ARM, DDR, IO}_PLL_LOCK] == 1.

4.Disable PLL bypass mode. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_BYPASS_FORCE] = 0.

5.Disable L2 cache dynamic clock gating. Set l2cpl310.reg15_power_ctrl[dynamic_clk_gating_en]=0.

6.Disable SCU standby mode. Set mpcore.SCU_CONTROL_REGISTER[SCU_standby_enable] = 0.

7.Disable Interconnect clock stop. Set slcr.TOPSW_CLK_CTRL[CLK_DIS] = 0.

8.Disable Cortex-A9 dynamic clock gating. Set cp15.power_control_register[dynamic_clock_gating] =0.

9. Enable all required peripheral devices, including DDR controller clocks.

10.Re-enable and serve interrupts. Execute cpsie if.

 

In the Xilinx SDK, all registers are unknows.


 

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