09-01-2018 03:56 AM - edited 09-01-2018 03:57 AM
I have 2x MICRON MT40A256M16GE DDR4 x16 256M chips connected to Zynq Ultrascale+ SoC PS DDR, finalizing the PCB layout design.
What are the rules for byte lane swapping in x16 device? Can I choose arbitrary the order of the byte lanes 1,2,3,4 between the 2 ICs not thinking about LDQS/LDM/DQ[0-7] / UDSQ/UDM/DQ[8-15] difference/order at all?
Byte lane 1 <=> IC2 UDSQ/UDM/DQ[8-15]
Byte lane 2 <=> IC1 LDQS/LDM/DQ[0-7]
Byte lane 3 <=> IC1 UDSQ/UDM/DQ[8-15]
Byte lane 4 <=> IC2 LDQS/LDM/DQ[0-7]
09-03-2018 12:19 PM
DDR4 Pin Swapping Restrictions
"DQ byte lane swapping is allowed. A byte lane includes any signals associated with the aligned 8-bits of DQ, such as DM, DQS, DQS_N, and DQ signals"
So, this is applicable also to a 16x memory, not just 8x? No need to take care of upper/lower byte lane order in 16x memory?
03-08-2019 08:37 AM
Sorry to dig up an old thread, but did you ever get an answer on byte lane swapping? Did you spin a board to test it out and if so, what were the results?
I have an issue that lane swapping might solve, but cant get anyone to respond.