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konze
Visitor
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Registered: ‎06-02-2017

Zynq UltraScale+ PS/PL ACP Reference Design

Hello there,

I‘m currently working with the Avnet UltraZed board and previously used the Zedboad. On the Zedboard I was able to use the AXI ACP port natively with an AXI master (generated by Vivado) on the PL. Now I would like to use the ACP port on the UltraZed however I could not find any reference Verilog design for the ACP port. And using my design from the Zedboard does not seem to work on the UltraZed.
So my question is, is there any reference design or comprehensive source for creating an AXI master using the ACP port on the PL.

Best regards,

konze
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konze
Visitor
Visitor
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Registered: ‎06-02-2017

Since there is still no reference design for the the AXI/ACP on the Zynq UltraScale+ I figured it out myself.

 

You can find a tutorial on how to setup an AXI/ACP Verilog design for the PL and how to access it on the PS under bare-metal and Linux on github:

 

https://github.com/k0nze/ultrazed_acp_example

 

 

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