I‘m currently working with the Avnet UltraZed board and previously used the Zedboad. On the Zedboard I was able to use the AXI ACP port natively with an AXI master (generated by Vivado) on the PL. Now I would like to use the ACP port on the UltraZed however I could not find any reference Verilog design for the ACP port. And using my design from the Zedboard does not seem to work on the UltraZed. So my question is, is there any reference design or comprehensive source for creating an AXI master using the ACP port on the PL.