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kba_haefner
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Registered: ‎10-11-2018

Zynq Ultrascale+ EMIO Trace Frequency - Bug in Zynq Ultrascale IP v3.3?

Hi,

I'm trying to setup a cpu trace connection via EMIO with Vivado2019.1 (Zynq Ultrascale+ IP v3.3)

I have configured the MPSCO IP-Core accordingly (trace enabled via EMIO, 32bits, DBG_TRACE frequency = 250MHz). I have also created an output clock with 250MHz and connected that to the "pl_ps_trace_clk" pin.

During implementation Vivado throws pulse_width violations for the PS8/PLPSTRACECLK pin. (Required 4ns, Actual 2ns). 

Why is that? I would expect a 2ns requirement since DBG_TRACE allows for up to 250MHz.

I've tested an identical setup with Vivado2018.3 (Zynq Ultrascale+ IP v3.2) and the implementation completed without violations. PS8/PLPSTRACECLK pulse width requirements were 2ns (what makes sense to me) and the cpu trace worked fine in the real world.

Could a Xilinx employee please comment on that topic.

Thanks a lot.

Regards,

Matthias

 

 

 

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ZYNQ_US_traceTest_db.PNG
ZYNQ_US_traceTest_violations.PNG
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jzblue
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Registered: ‎07-21-2020

same question here, is this a real issue? Thanks.

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