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Registered: ‎10-09-2019

Zynq Ultrascale+ MPSoC Clock Phase timing diagram clarification

I'm using Zynq Ultrascale+ MPSoC XCZU4EG-1SFVC784I in my Design. I'm interfacing the QSPI with a MICRON NOR Flash which only operates with CPHA = 0,(i.e it latches data in at rising edge and shifts data out at falling edge). So I want the MPSoC also to be operated in CPHA = 0 mode. According to Config(QSPI) register in the register reference site, only two modes are possible which are CPHA,CPOL = 0b00 and CPHA, CPOL = 0b11. I can operate the SoC in CPHA, CPOL = 0b00 configuration which should latch in data at the rising edge and shift out data at the falling edge.  

But the timing diagram mentioned in this link ( shows that for CPOL = 0, the data is being shifted at the rising edge. According to Config(QSPI) register if CPOL = 0, CPHA should also be 0, which should shift the data out at falling edge.  So, shouldn't TQSPICKO2 be the time between falling edge and the data out instead of the rising edge and data out? and TQSPIDCK should be the time between Data In and rising edge instead of Data in and Falling edge?

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