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Visitor
Visitor
1,997 Views
Registered: ‎07-02-2018

Zynq Ultrascale+ PL SYSMON DRP/System Management Wizard

I am trying to connect the SYSMON-4 primitive on the PL side to a linux driver that is implemented using the DRP interface.  Per the documentation in UG974 (v2018.2) UltraScale Architecture Libraries Guide the recommended method for instantiation is by using the IP Integrator.  I added the System Management Wizard (1.3) block to the design to instantiate the primitive, and selected the DRP interface.  

What I cannot figure out is how the DRP interface connects to the ZYNQ ULTRASCALE+ block.

I saw blog posts that talked about an AXI DRP bridge, but that block does not appear to be in my 2018.2 catalog.  I have also read through UG580 SYSMON User Guide, and UG1085 Zynq UltraScale+ Device TRM. Does anyone know how to connect this block?

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-04-2012

The PL sysmon block can be accessed directly from the PS using the APB interface. There is no need to connect it through another AXI interface. Refer to the TRM (UG1085).

For Linux DTS/driver information refer to this wiki page:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842163/ZynqMP+AMS

Regards,

Christophe

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Visitor
Visitor
1,933 Views
Registered: ‎07-02-2018

Christophe, 

Thank you for your response, but unfortunately I am still confused.  We are trying to use the PL SYSMON ADCs to measure off chip voltages. I believe we tried it just as you said, and we were not albe to read ADC data.  There is some confusion in the documentation about instationation of the SYSMONE4 primitive: 

The TRM has a schematic  (Figure 9-6) that shows a MUX that is driven by SYSMONE4 instantiation.  This schematic appears to show that the SYSMONE4 should not be instantiated in order to provide access to the PL SYSMON. This appears to contradict a statement in UG580 Pg 18. that says:

“It is not necessary to instantiate the SYSMON in a design to access the on-chip monitoring capability. However, if the SYSMON is not instantiated in a design, the only way to access this information is by using either the JTAG TAP or I2C. To allow access to the status registers (measurement results) from the interconnect logic, the SYSMON must be instantiated.”

If I do not instantiate the SYSMONE4 primitive, will I still be able to read the ADCs?  If the primitive is not instantiated, how are the pins connected to the ports of the primitive?

Thank you, 

Zach

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1,610 Views
Registered: ‎05-22-2013

Hi Zach,

I have the exact same issue. I need to instantiate the PS SYSMON in order to route the correct VAUX ports but then I only read 0 from the Linux AMS driver. Did you manage to solve this?

Thank you,

Christophe

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Contributor
Contributor
1,531 Views
Registered: ‎01-14-2015

Hi Zach, 

 

You might want to have a look at https://forums.xilinx.com/t5/Installation-and-Licensing/Looking-for-AXI-gt-DRP-bridge-installation-issue/td-p/964595

 

There is a sample project in XAPP1214 which has DRP bridge component. XAPP1214 also has steps to add this components to your custom design. I hope this helps. 

 

Thanks

-Prathamesh

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Moderator
Moderator
1,502 Views
Registered: ‎07-31-2012

Hi @zblack ,

We have SYSMON driver called AMS driver for both PL and PS SYSMON but via non-AXI as SYSMONs are hard IP in ZU+.

System Management Wizard is AXI based access to PL SYSMON for PS. There is no linux driver for system management wizard.

Using AMS driver as explained in my earlier email with no System Management Wizard instantiated in PL and required device tree

changes for external channels of vp/vn, vaux is the working solution.

Refer to attached system-user.dtsi snippet for channels to monitor.

 

/include/ "system-conf.dtsi"
/ {
};

&xilinx_ams{
   compatible = "xlnx,zynqmp-ams";
   status = "okay";
   interrupt-parent = <&gic>;
   interrupts = <0 56 4>;
   interrupt-names = "ams-irq";
   reg = <0x0 0xffa50000 0x0 0x800>;
   reg-names = "ams-base";
   #address-cells = <2>;
   #size-cells = <2>;
   #io-channel-cells = <1>;
   ranges;

   ams_ps: ams_ps@ffa50800 {
    compatible = "xlnx,zynqmp-ams-ps";
    status = "okay";
    reg = <0x0 0xffa50800 0x0 0x400>;
   };

   ams_pl: ams_pl@ffa50c00 {
    compatible = "xlnx,zynqmp-ams-pl";
    status = "okay";
    reg = <0x0 0xffa50c00 0x0 0x400>;
    xlnx,ext-channels {
      #address-cells = <1>;
     #size-cells = <0>;
     channel@5 {
      reg = <5>;
     };

     channel@6 {
      reg = <6>;
     };
                                };

    };
  };

Regards

Praveen


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1,497 Views
Registered: ‎05-22-2013

Hi Praveen,

What is the method to specify which FPGA bank the auxilary channels are connected to with the AMS driver?

Regards,
Christophe

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Observer
Observer
636 Views
Registered: ‎06-06-2018

Hi Christophe,

Did you manage to find out how to specify the FPGA bank the auxiliary channels are connected? I am also looking into this but unable to find any information. 

 

Regards,

Chee Yong

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620 Views
Registered: ‎05-22-2013

Hi Chee Yong,

No i never could find out, maybe this is not actually supported. In the end i connected the PL Sysmon to an AXI bus.

Christophe

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Visitor
Visitor
266 Views
Registered: ‎06-20-2019


We have SYSMON driver called AMS driver for both PL and PS SYSMON but via non-AXI as SYSMONs are hard IP in ZU+.

System Management Wizard is AXI based access to PL SYSMON for PS. There is no linux driver for system management wizard.

It turns out that the AXI interface is identical to the APB interface, so the AMS driver can be used with the system management wizard AXI.

What you need to do is to update the reg property for the "xlnx,zynqmp-ams-pl" device tree node to point to the "Master SYSMON" slice of the system management wizard interface instead of the "Slave 0 SYSMON" slice of the APB interface, i.e. do this:

&ams_pl {
   reg = <0xXXXXXXXX 0xXXXXX400 0x0 0x400>;
};

where 0xXXXXXXXXXXXXX000 is the base address of the system management wizard.

If you're using the FPGA manager, make sure to mark the xilinx_ams device node as disabled until the bitstream has been loaded to avoid lockups by accessing AXI too early.

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