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1,847 Views
Registered: ‎03-05-2018

Zynq Ultrascale PS MIO Support of Open-Drain or Open-Collector Outputs

Does the Zynq Ultrascale+ (ZU15EG)  either on PS MIO or PL I/O support true Open-Drain or Open-Collector

output drivers (YES or NO).

 

If; YES, please point to exact documents cause when looking in the data sheet, user guide, I/O selector guide, or

other documents one can not find reference to this output standard being supported on the PS-MIO or PL-I/O.

 

Yes "DONE" output is open-drain but that is a dedicated output.

 

Walter

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jmcclusk
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Registered: ‎02-24-2014

In the PL fabric, all the IO can support true open drain (by using a tri-state driver that drives a constant '0').   In the MIO  most will not, except for the I2C interfaces.    

 

From UG974:

 

obuft.png

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Registered: ‎03-05-2018

A tri-state buffer is not a true open-drain / open-collector with a single MOSFET or JFET correct?

 

waTer

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Registered: ‎03-05-2018

A constant zero being driven on an I2C bus can not support multiple master configuration in a true Wired-AND technology.

 

Walter

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jmcclusk
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Registered: ‎02-24-2014

it's not a true open drain, since there is a pull-up transistor that's always turned off.  There are also protection diodes connected to the Vcco bus as well.    But it's functionally equivalent to an open-drain output, withing the voltage limits of GND to Vcco.    If you are looking for a high voltage open-drain driver  (greater than 1.8 or 3.3V, then you'll need a discrete driver of some kind connected to the FPGA drivers).

 

With a tri-state driver with a constant zero,  the output has 2 possible states..    0 and Z..    this is the equivalent to open drain.

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komalcharan
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Registered: ‎10-09-2019

I think it is possible using the register MIO_MST_TRI0, MIO_MST_TRI1, MIO_MST_TRI2 or in the IOU_SLCR module. 

Reference:

https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

 

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