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jwaln770
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Registered: ‎04-29-2019

Zynq Ultrascale+ PS_REF_CLK RMS jitter requirements

The PS_REF_CLK input RMS clock jitter requirement is specified at a max of 3ps, but there is no phase noise frequency range.  Most clock vendors and device vendors specify RMS jitter from 12Khz to 20Mhz.   So, is there a phase noise frequency range that goes with the 3ps Max. rms jitter requirement?

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