i'm working with the zynq ultrascale+ MPSoC with the linux cadence spi driver.
I'm having problems with the 3 wire configuration of the SPI. I'm using the EMIO - pins as CS, SCLK, MOSI/MISO.
For 3 wire mode i need a type signal, so that my devices knows whether my MOSI/MISO - pin is an input or an output.
The problem is, that none of my signals can achieve that (see picture).
In the picture you can see the signals i get when running spi_write_then_read.
The first 16 bits are adress-bits with the read/write bit in front, the last 8 bits are the data bits i want to read.
CS is pin spi0_ss_o_n.
The type bit should be low during the writing process (first 16 bits) and high during reading (last 8 bits).
I know that there is no problem with connected device (which is a lmk04828).
I hope someone can help me with my problem.