hello, I'am debugging a board of our own manufacture，which use xczu9eg-ffvb1156-2-i.
But we meet very strange problem. Two Important PLLs never lock.
Refer to ug1085, I see the device has several plls
The pll for APU and RPU not locked(as shoiwn below),
xsct% rrd crf_apb pll_status
vpll_stable (Bits ): 1 dpll_stable (Bits ): 1
apll_stable (Bits ): 1 vpll_lock (Bits ): 0
dpll_lock (Bits ): 1 apll_lock (Bits ): 0
and I think this makes all the CPUs held in reset.
1 PS TAP
5 RPU (Reset)
6 Cortex-R5 #0 (RPU Reset)
7 Cortex-R5 #1 (RPU Reset)
8 APU (L2 Cache Reset)
9 Cortex-A53 #0 (APU Reset)
10 Cortex-A53 #1 (APU Reset)
11 Cortex-A53 #2 (APU Reset)
12 Cortex-A53 #3 (APU Reset)
It is strange that the dpll is locked, but apll and vpll does not.
We checked our all power, all are OK.
We checked PS_REF_CLK, it is in right freqency and has good quality.
We checked PS_POR_B , PS_SRST_B, and find no wrong.
Why the two PLLs not lock ?
How to make the two PLL lock ?
Could anyone do us a favour ?