11-07-2016 09:25 AM
I have this use-case:
Process running on CPU will allocate chunk of memory and will put certain addresses from it to pool (located in memory) of available addresses (some fifo). HW in PL will take addresses from here (virtual addresses) and DMA in HW will write some data at the address. Then it will push used address to different pool located in RAM and different thread would take them and work with them. After finishing the work, it would put the address back to pool of available ones. Everything should be as fast as possible.
Now the question:
Normally, pair of addresses would be needed - virtual for the program and physical for the DMA. This pair would have to be saved in the pool. In the new UltraScale architecture however, there is SMMU, so HW in PL can use virtual addresses and they will be translated to physical.
It is explicitly said in TRM, page 948:
"All high-performance interfaces into the FPD pass through the system memory
management unit (SMMU).
SMMU in the path of these high-performance PL interfaces provides the following support.
• Support for the use of virtual addresses (same address as is used by the software
application) in the PL masters.
• Protection as SMMU performs access checks for a transaction"
So virtual address could be used - no need for physical.. It would be truly marvelous, if I could operate only with one address (only half of bandwidth would be used). But how could it work?
There is debate at my team about this. Statement from TRM would imply, that somehow only one page table is used! But each process have his own table, right? So same virtual address maps to different physical addresses in different processes. So how can PL use the same address as is used by the SW? Conclusion of the debate was, that PL has to have it's own page table and that we will have to use pair of two virtual addresses - one for DMA (that one will get translated by SMMU) and one for application (that one will be pushed to pool of used addresses and used by the application to access the memory).
Is this conclusion correct? Does anybody knows more about how it really works?
11-07-2016 10:59 AM
just one clarification: >> So same virtual address maps to different physical addresses in different processes
this is reversed. There is one physical address in PL and different processes get different virtual addresses to the same physical address.
11-07-2016 11:50 AM
Yes, I meant it as you say - two virtual addresses that have same value do not usually map on the same physical address.
What do you mean by "There is one physical address in PL"? From TRM it seems, that PL now works with virtual addresses..
I wonder if it's possible to use same address space for one process and PL (or maybe one PL's interface) - it would be awesome, for example, if I could set SMMU to translate DRAM accesses on HPC0 with page table of certain process.