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abderrahim29
Participant
Participant
6,703 Views
Registered: ‎02-06-2013

Zynq Write to DDR from PL

Hello,

 

i'm trying to write data from a Custom-IP in the PL section of the Zynq to the DDR without using the ARM. The ARM should just give a "start command" but the main work should be done by the PL. After this the ARM should read the written data out of the DDR to control it.

 

I have already read the CTT-Guide, especially chapter 6 (http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/ug873-zynq-ctt.pdf). But in my point of view the main work / functionality is done by the ARM and is included in the c-code that appears in SDK.

 

And there is my problem. I don't want to use the ARM for this task and i'm sure that it is possible.

 

Therefore i created a Custom-IP with 1 AXI slave lite interface to get the "start command" from the processor and 1 AXI master interface that should write the data to the ddr. The slave port of my Custom-IP is connected to the M_AXI_GP0 port of the zynq through an AXI interconnect. The master port is connected to the S_AXI_HP0 port through another AXI interconnect.

 

I still integrated a VHDL-file to my Custom-IP that responds to the "start command" and generates some test data. But i really don't know how to write these data to the DDR now. I know the adress range from the DDR which correspond with the adress range of the S_AXI_HP0 port. Should i use the CDMA to connect my Custom-IP to the S_AXI_HP0 port instead of the AXI interconnect? It is essential for me to realize the data transfer in VHDL.

 

I hope that there is anybody who can help me. I'm looking for a solution since the beginning of this week and i have read so many files and scripts but i didn't find a solution until now.

 

Regards Abderrahim

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austin
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Scholar
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Registered: ‎02-27-2008

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ajasan
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Adventurer
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Registered: ‎03-31-2014

Hi, @abderrahim29

 

Did you find a solution for your problem?

 

I am trying to do a memory transfer that trasfers the memory content of DDR from one location to another, using PL.

 

From the Zynq IP block diagram, I understand that DDR controller is connected to AXI high speed ports of PL. I am not clear about how the connected AXI HP port to be driven in order to make the DDR transactions?

 

Can we do it using any IP , but PL only to do that, not PS.

 

Else, if I have to write custom RTL code to drive that AXI HP port, how to drive it? please help with any available documents/ suggestion.

 

Thanks,

Aj.

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shahumang999
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Registered: ‎10-30-2019

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