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peltier
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Registered: ‎08-24-2018

Zynq Z020 EMIO state before FPGA "loaded"

Hello,

 

I would like to know if it is possible to maintiain EMIO state in tri-state ,  until the FSBL finishes to write the bit file to the PL.

 

 

Thanks by advance.

 

Gilles Peltier

Senior embedded engineer.

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