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Registered: ‎07-25-2016

Zynq ZC702 - Flushing System-Cache 4.0 IP from PS side

Hi Everyone,


I'm designing a (starting point) design using the System Cache IP (vers 4.0) like in the one attached in figure (Vivado 2017.3). My kernel reads/writes through the system-cache, connected to the GP port. Once the computation is done, I obviously need to flush the cache content in order for the PS to utilize the correct data.


My idea was to control the execution of the kernel and check for its completion. Once I know that the kernel is done, I issue the Flush through the S_AXI_CTRL port of the cache. I read the documentation and I came up with this code (run in bare metal):

#define CACHE_BASE_ADDR 0x43C20000
#define CACHE_REG_FLUSH_HIGH 0b11100000000011100
#define CACHE_REG_FLUSH_LOW 0b11100000000011000
#define CACHE_REG_MEM_BARRIER 0b11100000001000000


volatile unsigned int *sys_cache = (unsigned int *) CACHE_BASE_ADDR;


	// Flush System Cache
for (i = 0; i < CACHE_SIZE; i++) {
	addr = i;

	Xil_Out32((u32) sys_cache + (u32) CACHE_REG_FLUSH_LOW, (u32) addr);
	Xil_Out32((u32) sys_cache + (u32) CACHE_REG_FLUSH_HIGH, (u32) 0);


In details, I write all the addresses that I would like to flush to the flush register. However, the documentation is not really clear and I might be missing something or doing everything simply in the wrong way.

Any idea on what could I be doing wrong?


Some further questions I have regarding the topic (and that might be related): why, in the documentation, the "Statistics Field for Control" is 1_1100_00xx_xxxx_xx00, and in the relative table is 1_11yy_yy00_0001_1x00? What do the "y"s stand for here?

How can I be sure that the flushing of one address is done before proceeding with the next address to flush?


Thank you in advance, Best,




Here is the block design:


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