05-29-2013 06:07 AM
I am working with a ZC706 test platform and am trying to establish a low latency data path for small amounts of data (~128 bits) from PS-to-PL BRAM. My current build has the following connection:
PS M_AXI_GP_1 <-AXI3-> AXI Interconnect (2.0) <-AXI4-> AXI BRAM Controller (3.0) <--> 32b wide (4kB total) Block Mem Gen (8.0)
My test application writes 4 32-bit values in BRAM and reads them back. I can do this successfully (see attached screenshot for AXI transaction picture). You can see that the time between transactions is 18 ticks (180ns at 100MHz AXI clock).
PG078 has extensive references to burst reads/writes for the AXI BRAM controller. I understand that AXI-lite does not support bursting, so none of my component interfaces are AXI-lite. However, I can only get single reads/writes with the XBram_WriteReg and XBram_ReadReg functions from the XilinxProcessorIPLib bram_v3_01_a example. How can I force a burst on the AXI GP port...am I missing some configuration item? Or, is this not possible without DMA controlling the transfer?
FYI, using Vivado 2013.1 w/ IP Integrator...
05-29-2013 08:05 AM
Attached is the applicable portion of the IP Integrator block diagram (no EDK on this one). Hopefully I don't get chastised too much for using Vivado 2013.1 w/ IP Integrator :) I actually haven't had too much trouble with it aside from minor GUI annoyances.
The PS-to-BRAM interface via M_AXI_GP1 works just fine. What I can't figure out is whether or not I can use that port to perform AXI read/write bursts directly into BRAM. I also have CDMA functional in this block design via S_AXI_HP0; however, I don't want to take the DMA configuration latency penalty every time I have to transfer my small, 128-bit data chunks.
My application is based on the hello_world sample app using standalone v3.09.
05-31-2013 10:46 AM
You have to change the mmu so that the bram address range is either configured as a memory device (coelessing would be enabled so writing to an incrementing address causes bursts) or configured as cachable space.
You would do this using the function Xil_SetTlbAttributes()