Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎07-01-2013

Zynq ZU11EG Pin assignments

I am in the process of choosing a board that has the ZU11-EG FPGA on it. I wanted to connect daughter card with USB 3.0 to the FMC connector.

How does the pin assignment work on the PS side of the FPGA? Are the pins general purpose? For instance if I have a display port, ethernet port and USB port, do each have to go to their own specific location or can I just assign the pins during the build?

Will a version of Linux automatically pick up device connected to these ports?


0 Kudos
1 Reply
Registered: ‎02-01-2013


PSU peripherals can use only certain MIO pins. MIO pins can bear only IO signals from certain PSU peripherals. In the Zynq MPSoC TRM (UG1085), search for the word "glance", then look at the "MIO Table at a Glance".  That table shows which MIO pins can be used for each peripheral.

Peripherals can also send IO pins through the PL (fabric) as EMIO. Sending IO in that way through the PL will use PL resources, but you do that when the benefit of using the PSU peripheral outweighs the loss of those resources. (MIO pins cannot be used to transport PL signals out of the chip.)

The specific peripherals you mention ("display port, ethernet port and USB port") have special IO's that (could) require the use of the limited GTR high-speed transceivers that are part of the PSU. In the TRM, see Chapter 29, PS-GTR Transceivers.

All of the PSU peripherals have existing driver support. Information from each specific design (such as: which MIO pins are used for IO, what are the essential clock frequencies, etc.) is fed forward from the hardware development tools into the software development tools.

-Joe G.


0 Kudos