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Registered: ‎11-15-2019

Zynq bare-metal: AXI DMA Interrupt issue

I am doing a bare-metal application on a Zynq device. I use an AXI DMA IP to move data from an AXI-Stream Data FIFO to the external DDR through the PS's HP port. Moving the data from the DDR to the FIFO (MM2S) works fine and generates the expected interrupt, through the wr_data_count bus in the FIFO i can see the number of written bytes is correct.

The problem comes when i try to move data from the FIFO to the DDR. For some reason both S2MM and MM2S interrupt flags activate. In the MM2S handler the interrupt assertion returns 0x0 so the interrupt is ignored, but on the s2mm handler the interrupt id is 0x5000 which means the flags for IRQ_IOC and IRQ_ERROR are activated. I then read the DDR to check if the data has been transferred but it hasn't. I based my code on the xaxidma_simple_intr.c. I thought it might be a problem with tlast and tkeep but i have been trying to change them with no success. I also maintained the DMA's tvalid to '1' but also no result. The data i move to the FIFO from the DDR is just a sequence of 2 byte words incrementing by 1 with each address (16b DDR). For now i left tkeep and tlast activated in the FIFO.

I'm working on a Cora Z7 board (1 core). I will add an image of my design, there some counters and GPIOS but that is for something else which works fine.

Any help will be gladly appreciated.

design_1.png
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