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Advisor
Advisor
9,088 Views
Registered: ‎02-12-2013

Zynq configuration size

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Hello,

 

Can someone tell me where to find the bitfile sizes for Zynq devices?

 

  Pete

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Community Manager
Community Manager
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Registered: ‎07-23-2012
Hi,

The bitfile size for Zynq devices is approximately equal to the FPGA device's (present on the PL) bitstream size.

For example, let us consider XC7Z020. This Zynq device has XC7A100T on PL side. Hence the size of the bitfile for XC7Z020 would be ~30 Mb as per UG470 Table 1-1.

Regards,
Krishna
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Moderator
Moderator
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Registered: ‎06-05-2013

Hi,

The size of bitstream depends upon the resources you have use.

Check the following user guide

http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

 

Thanks

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Advisor
Advisor
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Registered: ‎02-12-2013
Can you give me a page number or section with details on calculating config data size?

I am interested for config time calculations. We want to do context switches with PL reconfig.

Thanks

Pete
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Advisor
Advisor
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Registered: ‎02-12-2013
 
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Community Manager
Community Manager
12,356 Views
Registered: ‎07-23-2012
Hi,

The bitfile size for Zynq devices is approximately equal to the FPGA device's (present on the PL) bitstream size.

For example, let us consider XC7Z020. This Zynq device has XC7A100T on PL side. Hence the size of the bitfile for XC7Z020 would be ~30 Mb as per UG470 Table 1-1.

Regards,
Krishna
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2012

The boot ROM supports configuration from four different slave interfaces:

• Quad-SPI

• NAND

• NOR flash

• SD card

Additionally Zynq-7000 devices can be programmed via a JTAG. This section details features of each

configuration interface. For details on the specific devices Xilinx recommends for each boot

interface please refer to AR 50991

http://www.xilinx.com/support/answers/50991.htm.

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Advisor
Advisor
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Registered: ‎02-12-2013

smarell,

 

It sounds like calculating configuration time for the PL (fpga) side of a Zynq device is an indirect activity.

 

1. Look at the size of the PL on the particular Zynq device.

2. Find a regular 7 Series device with about the same size.

3. Look up the bitfile size of that similar 7 Series device in UG470, Table 1-1, ~ 30Mb for the XC7Z020.

4. I have seen some numbers saying that the Zynq Arm processor can configure the PL at 300Mb/s.  Configuration time would be about 100Ms.

5. Partial reconfiguration would then be a fraction of that time depending on how much of the chip you reload.

 

I think that answers my question.  Thanks everybody.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-13-2011

Are you looking for the PL configuration bitstream lenths?  Please see the Zynq Technical Reference Manual (UG585 v1.7), Table 21-2, page 618.  

 

http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

You can also use the search tool to look for "PL Bitstream Lengths".

 

 

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Advisor
Advisor
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Registered: ‎02-12-2013

Thanks Bryan,

 

That does answer my question. Table 21-2 is now on page 647 but that is what I needed.

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