02-19-2016 07:09 AM
I'm relatively new to embedded processor design and am having issues using the gmii_to_rgmii IP. My objective is to receive rgmii from the PS_GEM1 and link it via EMIO to the PS.
I am able to implement the design, but I receive critical warnings. These are warnings I normally receive when I constrain a signal that I forgot to make external.
[Common 17-55] 'set_property' expects at least one object. [constrs_1/new/PL_IO_constraint.xdc":681]
[Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-rise_to [get_clocks -of_objects [get_ports RGMII_rxc]]'.
Additionally, I noticed some messages in my tcl console that lead me to suspect even more that my signals are not being set to external properly.
WARNING: [BD 41-1306] The connection to interface pin /gmii_to_rgmii_0/rgmii_rxc is being overridden by the user. This pin will not be connected as a part of interface connection RGMII
Any ideas as to why I'm receiving these warnings? Thanks!
02-19-2016 07:34 PM
02-19-2016 07:34 PM
02-22-2016 11:23 PM
would that be possible to send the design?
02-23-2016 10:37 AM
I'm glad you reference that design, it has helped me a lot. I believe you are correct in that there is something wrong with my constraints file. I have found constraints documentation vivado provided for this IP: http://www.xilinx.com/support/documentation/ip_documentation/gmii_to_rgmii/v3_0/pg160-gmii-to-rgmii.pdf
Strangely, I am receiving errors for both these constraint commands and my external pin constraints. For example, these commands:
set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]
set_property PACKAGE_PIN U26 [get_ports rgmii_rxc]
create_clock -period 5.000 -name clkin -add [get_nets clkin]
create_clock -period 8.000 -name rgmii_rxc -add [get_ports rxc]
Results in the critical warnings:
[Common 17-55] 'set_property' expects at least one object. ["constrs_1/new/PL_IO_constraint.xdc":4]
[Common 17-55] 'set_property' expects at least one object. ["constrs_1/new/PL_IO_constraint.xdc":5]
[Vivado 12-1387] No valid object(s) found for create_clock constraint with option '-objects [get_nets clkin]'. ["constrs_1/new/PL_IO_constraint.xdc":7]
[Vivado 12-1387] No valid object(s) found for create_clock constraint with option '-objects [get_ports rgmii_rxc]'. ["constrs_1/new/PL_IO_constraint.xdc":8]
I don't understand why neither clkin nor rgmii_rxc are valid objects since I have them connected?
02-25-2016 07:33 AM
The issue was that in my constraint file, I was providing the name I saw on the block diagram (in lower case letters), the actual port name when viewed in properties was upper case. Thanks for the help!