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Adventurer
Adventurer
10,305 Views
Registered: ‎02-19-2016

Zynq gmii_to_rgmii connection issues

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Vivado 2015.2

 

I'm relatively new to embedded processor design and am having issues using the gmii_to_rgmii IP.  My objective is to receive rgmii from the PS_GEM1 and link it via EMIO to the PS.

 

block_diagram.JPG

 

I am able to implement the design, but I receive critical warnings.  These are warnings I normally receive when I constrain a signal that I forgot to make external.

[Common 17-55] 'set_property' expects at least one object. [constrs_1/new/PL_IO_constraint.xdc":681]

[Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-rise_to [get_clocks -of_objects [get_ports RGMII_rxc]]'.

 

 

Additionally, I noticed some messages in my tcl console that lead me to suspect even more that my signals are not being set to external properly.

WARNING: [BD 41-1306] The connection to interface pin /gmii_to_rgmii_0/rgmii_rxc is being overridden by the user. This pin will not be connected as a part of interface connection RGMII

 

 

Any ideas as to why I'm receiving these warnings?  Thanks!

 

 

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Contributor
Contributor
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Registered: ‎12-09-2015

Re: Zynq gmii_to_rgmii connection issues

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http://www.fpgadeveloper.com/2015/12/using-axi-ethernet-subsystem-and-gmii-to-rgmii-in-a-multi-port-ethernet-design.html

please go through this design and let me know whether it was helpful....
The problem is with your constrain file..

View solution in original post

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Adventurer
Adventurer
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Registered: ‎02-19-2016

Re: Zynq gmii_to_rgmii connection issues

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I should mention that this is the zynq 7000 zc702.

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Contributor
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Registered: ‎12-09-2015

Re: Zynq gmii_to_rgmii connection issues

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http://www.fpgadeveloper.com/2015/12/using-axi-ethernet-subsystem-and-gmii-to-rgmii-in-a-multi-port-ethernet-design.html

please go through this design and let me know whether it was helpful....
The problem is with your constrain file..

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: Zynq gmii_to_rgmii connection issues

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hi

 

would that be possible to send the design?

 

--hs

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Adventurer
Adventurer
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Registered: ‎02-19-2016

Re: Zynq gmii_to_rgmii connection issues

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I'm glad you reference that design, it has helped me a lot.  I believe you are correct in that there is something wrong with my constraints file.  I have found constraints documentation vivado provided for this IP: http://www.xilinx.com/support/documentation/ip_documentation/gmii_to_rgmii/v3_0/pg160-gmii-to-rgmii.pdf

 

Strangely, I am receiving errors for both these constraint commands and my external pin constraints.  For example, these commands:


set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]
set_property PACKAGE_PIN U26 [get_ports rgmii_rxc]

create_clock -period 5.000 -name clkin -add [get_nets clkin]
create_clock -period 8.000 -name rgmii_rxc -add [get_ports rxc]

 

Results in the critical warnings:

[Common 17-55] 'set_property' expects at least one object. ["constrs_1/new/PL_IO_constraint.xdc":4]
[Common 17-55] 'set_property' expects at least one object. ["constrs_1/new/PL_IO_constraint.xdc":5]
[Vivado 12-1387] No valid object(s) found for create_clock constraint with option '-objects [get_nets clkin]'. ["constrs_1/new/PL_IO_constraint.xdc":7]
[Vivado 12-1387] No valid object(s) found for create_clock constraint with option '-objects [get_ports rgmii_rxc]'. ["constrs_1/new/PL_IO_constraint.xdc":8]

 

I don't understand why neither clkin nor rgmii_rxc are valid objects since I have them connected? 

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Adventurer
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Registered: ‎02-19-2016

Re: Zynq gmii_to_rgmii connection issues

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The issue was that in my constraint file, I was providing the name I saw on the block diagram (in lower case letters), the actual port name when viewed in properties was upper case. Thanks for the help!

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