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zpac
Adventurer
Adventurer
7,659 Views
Registered: ‎03-03-2015

Zynq hard DMA and transfers from DDR to PL peripherals

Hi, all!

 

I've been looking at the hard DMA, featured in the Zynq PS. I intend to use it the same way I'd use a soft AXI DMA in the PL, in order to deliver data to other IP blocks.

From the information I was able to find (correct me, if I'm wrong), it seems that the hard DMA offers 8 concurrent channels, of which 4 of them can be used to send/receive data from the PL.

 

When trying to create a simple test design, a few questions occured to me:

1) I couldn't quite figure out where exactly does the transfer from the PS to the PL takes place. While customizing the Zynq IP block (under the "PS-PL configuration" tab), up to 4 DMA interfaces can be enabled. My initial thought was that the data goes through these interfaces into the PL, according to what DMA channel is being used. However, I read somewhere that the DMA channels are supposed to use the GP ports? So where exactly does the data go through? The GP ports? or the DMA interfaces?

 

2) If the data does come through the GP ports, is it possible to use an AXI data mover to convert the data from AXI full to AXI stream, just like the soft AXI DMA would do? Even though the AXI data mover has no MM2S AXI slave interfaces and therefore has no base_address recognizable from the PS?

 

Thanks in advance.

 

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2 Replies
bwiec
Xilinx Employee
Xilinx Employee
7,647 Views
Registered: ‎08-02-2011

Hello,

 

1) If you look at the address map in the TRM, you can see the addresses that are accessible to the DMAC (the 'Other Bus Masters column). From that, you can see it can access the PL via GP0 or GP1 through addresses 0x4000_0000 to BFFF_FFFF. The additional DMAC stuff you can enable in the PS7 block in IPI are for flow control.

 

2) No, you wouldn't use the datamover because it's a bus master, not a slave. You could use something like the AXI Stream FIFO which has a slave AXI4 interface (which would accept data from the DMA) and a master stream interface through which that data could be sent to your peripherals that accept streaming data.

 

 

www.xilinx.com
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zpac
Adventurer
Adventurer
7,588 Views
Registered: ‎03-03-2015

Hello, @bwiec.

 

Thank you, once again, for your reply. Really do appreciate all your help.

 

I've been messing around with the AXI Fifo, like you suggested. I was un-aware that the AXI Stream FIFO was also able to receive data via AXI4 full. However, I'm not being able to get the FIFO to receive any data via AXI4-full, neither from the DMAC or from 'normal access' (using the driver's examples).

 

- While running XLlFifo_polling_example.c (which uses the functions already provided in xllfifo.h), it appears that the program hangs when trying to write the 32 bit word to the AXI4 address (done in function "XLlFifo_TxPutWord"). From what I can conclude from a couple of ILA probes, it appears that only the initial transactions regarding register initializations (interrupt enables, etc.) are getting thorugh to the IP.

 

- I also figured I should try the direct register read/write programming sequence provided in the product guide (PG080), since I figured that it would be easier to directly mess around with the register addresses once the DMAC is thrown into the mix (instead of using the TxSend/RxReceive functions, which already need the data address in the memory). However, the program also hangs when trying to setup a transfer to the FIFO (more specifically, the first hang occurs when accessing the TDFV register).

 

I'm guessing I'm missing some trivial detail in my design, since the IP's own example won't work properly? My design only consists of the FIFO connected to the GP Ports (using both AXI Lite and AXI Full interfaces). I also tried to connect an AXI-4 Stream data FIFO to the original FIFO, just to have a loopback connection in the AXI-Stream domain. The problems persisted, though.

 

Thanks, once again.

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